Satoshi Shigematsu

35 papers A 1B 2C 1Journal 15Unranked 16

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	Hierarchical Scheduling with FPGA-based Accelerator for Flexible 5G Mobile Networks. VTC Spring Yuki Arikawa, Takeshi Sakamoto, Satoshi Shigematsu
2020	—	`conf`	Miniature Optical Connector with Magnetic Physical Contact. OFC Kota Shikama, Norio Sato, Atsushi Aratake, Satoshi Shigematsu, Takeshi Sakamoto
2019	—	`conf`	5G R&D Activities for High Capacity Technologies with Ultra High-Density Multi-Band and Multi-Access Layered Cells. VTC Spring Morihiko Minowa, Hiroyuki Seki, Yukihiko Okumura, Satoshi Suyama, Jun Terada, Satoshi Shigematsu, Yasushi Takatori, Hiroaki Asano, Yukio Hirano, Yasushi Yamao, Fumiyuki Adachi, Masataka Nakazawa
2019	J	`jnl`	Proximity Gettering Design of Hydrocarbon-Molecular-Ion-Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors. Sensors Kazunari Kurita, Takeshi Kadono, Satoshi Shigematsu, Ryo Hirose, Ryosuke Okuyama, Ayumi Onaka-Masada, Hidehiko Okuda, Yoshihiro Koga
2018	—	`conf`	Contention-Less Scheduling-Free Torus Optical Network Comprising Thousands of Nodes. ECOC Salah Ibrahim, Toshikazu Hashimoto, Satoshi Shigematsu
2018	B	`conf`	Throughput Enhancement with Hardware Accelerated Resource Scheduler in Low-Latency 5G Systems. PIMRC Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu
2017	J	`jnl`	A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda
2016	—	`conf`	High-speed radio-resource scheduling for 5G ultra-high-density distributed antenna systems. WCSP Yuki Arikawa, Hiroyuki Uzawa, Takeshi Sakamoto, Satoshi Shigematsu
2015	—	`conf`	A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table. ISPACS Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda
2015	—	`conf`	Data transmission scheme for enhancing effective downlink bandwidth in 5G mobile fronthaul with TDM-PON. ECOC Hiroyuki Uzawa, Yuki Arikawa, Kenji Kawai, Satoshi Shigematsu
2015	C	`conf`	High-speed sorted-table search scheme for network processing. APCC Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Satoshi Shigematsu
2015	—	`conf`	Practical resource scheduling in massive-cell deployment for 5G mobile communications systems. ISPACS Yuki Arikawa, Kenji Kawai, Hiroyuki Uzawa, Satoshi Shigematsu
2015	J	`jnl`	Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip. IEICE Trans. Electron. Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata
2014	—	`conf`	A novel DBA scheme for TDM-PON based mobile fronthaul. OFC Takayoshi Tashiro, Shigeru Kuwano, Jun Terada, Tomoaki Kawamura, Nobuyuki Tanaka, Satoshi Shigematsu, Naoto Yoshimoto
2014	—	`conf`	Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoC. ReConFig Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu
2012	J	`jnl`	Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu
2012	B	`conf`	Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs. FPL Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano
2010	J	`jnl`	Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. IEEE J. Solid State Circuits Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida
2010	—	`conf`	Fusion of MEMS and circuits. ISSCC Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner
2008	—	`conf`	A Fingerprint Sensor with Impedance Sensing for Fraud Detection. ISSCC Toshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi
2007	J	`jnl`	Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI. IEICE Trans. Electron. Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi
2006	J	`jnl`	Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Trans. Electron. Satoshi Shigematsu, Koji Fujii, Hiroki Morimura, Takahiro Hatano, Mamoru Nakanishi, Namiko Ikeda, Toshishige Shimamura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi
2005	J	`jnl`	Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier. IEICE Trans. Electron. Satoshi Shigematsu, Hiroki Morimura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi
2002	—	`conf`	A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification. CICC Koji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi
2002	—	`conf`	A Fingerprint Verification Algorithm Using the Differential Matching Rate. ICPR (3) Takahiro Hatano, Takuya Adachi, Satoshi Shigematsu, Hiroki Morimura, Shigehiko Onishi, Yukio Okazaki, Hakaru Kyuragi
2002	J	`jnl`	A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs. IEEE J. Solid State Circuits Hiroki Morimura, Satoshi Shigematsu, Toshishige Shimamura, Katsuyuki Machida, Hakaru Kyuragi
2002	—	`conf`	Fingerprint Image Enhancement by Pixel-Parallel Processing. ICPR (3) Namiko Ikeda, Mamoru Nakanishi, Koji Fujii, Takahiro Hatano, Satoshi Shigematsu, Takuya Adachi, Yukio Okazaki, Hakaru Kyuragi
2000	J	`jnl`	A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors. IEEE J. Solid State Circuits Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida
1999	A	`conf`	A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells. ISLPED Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka
1999	J	`jnl`	A single-chip fingerprint sensor and identifier. IEEE J. Solid State Circuits Satoshi Shigematsu, Hiroki Morimura, Yasuyuki Tanabe, Takuya Adachi, Katsuyuki Machida
1999	—	`conf`	Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. ASP-DAC Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka
1997	J	`jnl`	A 0.5-V MTCMOS/SIMOX logic gate. IEEE J. Solid State Circuits Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya
1997	J	`jnl`	A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE J. Solid State Circuits Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada
1996	J	`jnl`	A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application. IEEE J. Solid State Circuits Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada
1995	J	`jnl`	1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J. Solid State Circuits Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada