Satoshi Ohtake

60 papers A 3B 3C 7Misc 5Journal 10Unranked 32

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	A Method of Controlling Devices Remotely in Online Embedded System Engineer Training. ICCE-Taiwan Toshiyuki Haramaki, Satoshi Ohtake
2023	—	`conf`	Field Monitoring System for Frost Damage Warning and Quality Difference Analysis of Tea Leaves. ICCE-Taiwan Shunsuke Mukai, Satoshi Ohtake
2023	—	`conf`	Hardware Implementation of Constant Monitoring System of Fetal Heart Sounds. ICCE-Taiwan Funakoshi Miyabi, Satoshi Ohtake
2023	—	`conf`	Vibration Measurement Experiment of Rails at Shinkansen Rail Yard in Kumamoto. GCCE Shunsuke Mukai, Satoshi Ohtake
2022	—	`conf`	A robust method of IC seating inspection in burn-in sockets using Hough transform. ICCE-TW Tsuneo Kagawa, Masaya Ikemoto, Satoshi Ohtake
2021	C	`conf`	Vibration Measurement of Signal Bonds for Shinkansen. ICCE Yuki Echigo, Satoshi Ohtake
2020	—	`conf`	A Warning System with Multiple Sensors for Avoiding Collision of Bicycles. ICCE-TW Kotaro Iwamoto, Satoshi Ohtake
2020	C	`conf`	Temperature Monitoring in Shinkansen Signal and Communication House. ICCE Yui Uehara, Satoshi Ohtake
2019	—	`conf`	A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures. ATS Yushiro Hiramoto, Satoshi Ohtake, Hiroshi Takahashi
2019	—	`conf`	A Koji Temperature Monitoring System. ICCE-TW Yui Uehara, Satoshi Ohtake, Takayuki Karyu
2019	C	`conf`	Factory Environment Monitoring: A Japanese Tea Manufacturer's Case. ICCE Yui Uehara, Satoshi Ohtake
2019	—	`conf`	Monitoring Sake Brewing Processes with Compact Wireless Sensors. ICCE-Berlin Yui Uehara, Satoshi Ohtake, Takamoto Fukura
2018	Misc	`conf`	A Method of Hardware-Trojan Detection Using Design Verification Techniques. CISIS Yushiro Hiramoto, Satoshi Ohtake
2017	—	`conf`	An approach to LFSR-based X-masking for built-in self-test. LATS Satoshi Ohtake, Daichi Shimazu
2015	C	`conf`	A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model. DDECS Shuichi Sato, Satoshi Ohtake
2015	C	`conf`	A Method of Diagnostic Test Generation for Transition Faults. PRDC Renji Ono, Satoshi Ohtake
2015	—	`conf`	A method of LFSR seed generation for hierarchical BIST. IDT Kosuke Sawaki, Satoshi Ohtake
2015	—	`conf`	A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults. LATS Takanori Moriyasu, Satoshi Ohtake
2013	Misc	`conf`	A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG. CISIS Takanori Moriyasu, Satoshi Ohtake
2011	J	`jnl`	Delay Testing: Improving Test Quality and Avoiding Over-testing. Inf. Media Technol. Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
2011	J	`jnl`	Delay Testing: Improving Test Quality and Avoiding Over-testing. IPSJ Trans. Syst. LSI Des. Methodol. Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda
2011	B	`conf`	F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. ETS Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
2011	J	`jnl`	F-Scan: A DFT Method for Functional Scan at RTL. IEICE Trans. Inf. Syst. Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
2010	J	`jnl`	A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Trans. Inf. Syst. Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
2010	C	`conf`	A synthesis method to propagate false path information from RTL to gate level. DDECS Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
2010	—	`conf`	Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
2010	A	`conf`	Constrained ATPG for functional RTL circuits using F-Scan. ITC Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara
2010	—	`conf`	Enabling False Path Identification from RTL for Reducing Design and Test Futileness. DELTA Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
2009	Misc	`conf`	A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. VTS Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
2009	—	`conf`	Fast false path identification based on functional unsensitizability using RTL information. ASP-DAC Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
2008	J	`jnl`	Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. IEICE Trans. Inf. Syst. Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara
2008	—	`conf`	Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
2007	J	`jnl`	Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Trans. Inf. Syst. Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara
2007	A	`conf`	Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
2007	—	`conf`	False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. ATS Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara
2006	C	`conf`	A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. VLSI-SoC Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2006	—	`conf`	Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. VLSI-SoC (Selected Papers) Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2006	—	`conf`	Design for Testability of Software-Based Self-Test for Processors. ATS Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
2006	—	`conf`	Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell
2006	—	`conf`	Low-Cost Hardening of Image Processing Applications Against Soft Errors. DFT Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara
2005	—	`conf`	A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
2005	B	`conf`	Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. ETS Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2005	—	`conf`	Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
2004	B	`conf`	A design methodology to realize delay testable controllers using state transition information. ETS Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2004	J	`jnl`	New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. J. Electron. Test. Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
2003	A	`conf`	A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. DATE Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara
2003	—	`conf`	Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. Asian Test Symposium Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
2002	Misc	`conf`	A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. VTS Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa
2002	J	`jnl`	A nonscan DFT method for controllers to provide complete fault efficiency. Syst. Comput. Jpn. Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
2002	—	`conf`	Design for Two-Pattern Testability of Controller-Data Path Circuits. Asian Test Symposium Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara
2001	—	`conf`	A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. ASP-DAC Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara
2001	—	`conf`	Design for Hierarchical Two-Pattern Testability of Data Paths. Asian Test Symposium Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara
2001	Misc	`conf`	Testable Design of Sequential Circuits with Improved Fault Efficiency. VLSI Design Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara
2000	J	`jnl`	A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency. J. Electron. Test. Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
2000	—	`conf`	A non-scan DFT method at register-transfer level to achieve complete fault efficiency. ASP-DAC Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara
1999	—	`conf`	A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. Asian Test Symposium Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
1999	—	`conf`	New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. Asian Test Symposium Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
1998	—	`conf`	A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. Asian Test Symposium Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
1997	J	`jnl`	A sequential circuit structure with combinational test generation complexity and its application. Syst. Comput. Jpn. Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki
1997	—	`conf`	Sequential Test Generation Based on Circuit Pseudo-Transformation. Asian Test Symposium Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara