Satoru Tanoi - RankMe

12 papers A 1Journal 7Unranked 4

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Design of an Analog Integrated Circuit Solving the Two-Armed Bandit Problem in 180-nm CMOS. AICAS Kohei Mori, Kazuyuki Wada, Kawori Sekine, Shinsuke Hara, Satoru Tanoi, Akifumi Kasamatsu
2024	—	`conf`	A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs. CICC Shunichi Kubo, Yuji Gendai, Satoshi Miura, Shinsuke Hara, Satoru Tanoi, Akifumi Kasarnatsu, Takeshi Yoshida, Satoshi Tanaka, Shuhei Arnakawa, Minoru Fujishlrna
2021	—	`conf`	A 76-Gbit/s 265-GHz CMOS Receiver. A-SSCC Shinsuke Hara, Ruibing Dong, Sangyeop Lee, Kyoya Takano, Naoya Toshida, Satoru Tanoi, Tatsuo Hagino, Mohamed H. Mubarak, Norihiko Sekine, Issei Watanabe, Akifumi Kasamatsu, Kunio Sakakibara, Shunichi Kubo, Satoshi Miura, Yohtaro Umeda, Takeshi Yoshida, Shuhei Amakawa, Minoru Fujishima
2014	J	`jnl`	A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs. IEICE Trans. Electron. Satoru Tanoi, Tetsuo Endoh
2012	J	`jnl`	A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS. IEICE Trans. Electron. Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2012	J	`jnl`	Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique. IEICE Electron. Express Sang-yeop Lee, Hiroyuki Ito, Satoru Tanoi, Noboru Ishihara, Kazuya Masu
2011	—	`conf`	A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. ISOCC Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu
2005	J	`jnl`	RF-CMOS Implementation of UWB Transceivers and Its Application to Video Transmission. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akifumi Kasamatsu, Akio Tanaka, Hiroshi Kodama, Satoru Tanoi, Yasuhiro Kaizaki, Juichi Nakada, Masami Hagio, Yoshiaki Kuraishi, Keren Li, Hitoshi Utagawa, Toshiaki Matsui, Ryuji Kohno
1998	A	`conf`	BIST: required for embedded DRAM. ITC Satoru Tanoi
1997	J	`jnl`	On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM. IEEE J. Solid State Circuits Satoru Tanoi, Yasuhiro Tokunaga, Tetsuya Tanabe, Kazuhiko Takahashi, Atsuhiko Okada, Masahiro Itoh, Yoshiki Nagatomo, Yoshio Ohtsuki, Masaru Uesugi
1996	J	`jnl`	A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. IEEE J. Solid State Circuits Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi
1994	J	`jnl`	A 32-bank 256-Mb DRAM with cache and TAG. IEEE J. Solid State Circuits Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi