Sasindu Wijeratne

35 papers A 2B 2C 3Misc 1Journal 17Unranked 10

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Accelerating MTTKRP for sparse tensor decomposition on GPUs. J. Parallel Distributed Comput. Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2026	J	`jnl`	System-Level Performance Modeling of Photonic In-Memory Computing. CoRR Jebacyril Arockiaraj, Sasindu Wijeratne, Sugeet Sunder, Md. Abdullah-Al Kaiser, Akhilesh Jaiswal, Ajey P. Jacob, Viktor K. Prasanna
2025	B	`conf`	AMPED: Accelerating MTTKRP for Billion-Scale Sparse Tensor Decomposition on Multiple GPUs. ICPP Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2025	J	`jnl`	AMPED: Accelerating MTTKRP for Billion-Scale Sparse Tensor Decomposition on Multiple GPUs. CoRR Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2025	J	`jnl`	Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU. CoRR Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2025	J	`jnl`	Predictive Performance of Photonic SRAM-based In-Memory Computing for Tensor Decomposition. CoRR Sasindu Wijeratne, Sugeet Sunder, Md. Abdullah-Al Kaiser, Akhilesh Jaiswal, Clynn Mathew, Ajey P. Jacob, Viktor K. Prasanna
2025	—	`conf`	System-Level Performance Modeling of Photonic In-Memory Computing. HPEC Jebacyril Arockiaraj, Sasindu Wijeratne, Sugeet Sunder, Md. Abdullah-Al Kaiser, Akhilesh Jaiswal, Ajey P. Jacob, Viktor K. Prasanna
2024	—	`conf`	Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU $\mathcal{X}_{(d)}$. IEEECONF Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2024	J	`jnl`	PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images. CoRR Sasindu Wijeratne, Bingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart
2024	—	`conf`	Predictive Performance of Photonic SRAM-Based in-Memory Computing for Tensor Decomposition. HPEC Sasindu Wijeratne, Sugeet Sunder, Md. Abdullah-Al Kaiser, Akhilesh Jaiswal, Clynn Mathew, Ajey P. Jacob, Viktor K. Prasanna
2024	—	`conf`	Sparse MTTKRP Acceleration for Tensor Decomposition on GPU. CF Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2024	J	`jnl`	Sparse MTTKRP Acceleration for Tensor Decomposition on GPU. CoRR Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2023	A	`conf`	Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA. FPGA Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna
2023	C	`conf`	Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. SBAC-PAD Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2023	J	`jnl`	Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. CoRR Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2023	B	`conf`	Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. FPL Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna
2023	J	`jnl`	Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. CoRR Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna
2023	J	`jnl`	Graph Neural Network for Accurate and Low-complexity SAR ATR. CoRR Bingyi Zhang, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart
2022	C	`conf`	Estimating the Impact of Communication Schemes for Distributed Graph Processing. ISPDC Tian Ye, Sanmukh R. Kuppannagari, César A. F. De Rose, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2022	—	`conf`	Modeling the Energy Efficiency of GEMM using Optical Random Access Memory. HPEC Bingyi Zhang, Akhilesh R. Jaiswal, Clynn Mathew, Ravi Teja Lakkireddy, Ajey P. Jacob, Sasindu Wijeratne, Viktor K. Prasanna
2022	—	`conf`	Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA. HPEC Sasindu Wijeratne, Akhilesh R. Jaiswal, Ajey P. Jacob, Bingyi Zhang, Viktor K. Prasanna
2022	J	`jnl`	Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA. CoRR Sasindu Wijeratne, Akhilesh R. Jaiswal, Ajey P. Jacob, Bingyi Zhang, Viktor K. Prasanna
2022	C	`conf`	Towards Programmable Memory Controller for Tensor Decomposition. DATA Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna
2022	J	`jnl`	Towards Programmable Memory Controller for Tensor Decomposition. CoRR Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna
2021	J	`jnl`	A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. CoRR Ruizhi Zhang, Sasindu Wijeratne, Yang Yang, Sanmukh R. Kuppannagari, Viktor K. Prasanna
2021	Misc	`conf`	Programmable FPGA-based Memory Controller. HOTI Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor K. Prasanna
2021	J	`jnl`	Programmable FPGA-based Memory Controller. CoRR Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor K. Prasanna
2021	—	`conf`	Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. HPEC Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2021	J	`jnl`	Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. CoRR Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna
2021	J	`jnl`	Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks. CoRR Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual
2020	—	`conf`	A High Throughput Parallel Hash Table on FPGA using XOR-based Memory. HPEC Ruizhi Zhang, Sasindu Wijeratne, Yang Yang, Sanmukh R. Kuppannagari, Viktor K. Prasanna
2019	A	`conf`	Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. FPGA Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual
2019	J	`jnl`	Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. CoRR Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual
2018	—	`conf`	Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks. ASAP Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual
2017	—	`conf`	High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. ASAP Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual