Sarvesh H. Kulkarni

15 papers A* 1A 2Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2017 J jnl
A 0.9-μm
IEEE J. Solid State Circuits
Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya
2016 — conf
A 0.9um
VLSI Circuits
Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang
2016 J jnl
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits
Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang
2015 — conf
Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process.
VLSIC
Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang
2010 J jnl
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m
IEEE J. Solid State Circuits
Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang
2008 J jnl
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.
IEEE J. Solid State Circuits
Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
2008 J jnl
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw
2007 — conf
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.
ISSCC
Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr
2006 A conf
A statistical framework for post-silicon tuning through body bias clustering.
ICCAD
Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw
2006 J jnl
Power Distribution Techniques for Dual VDD Circuits.
J. Low Power Electron.
Sarvesh H. Kulkarni, Dennis Sylvester
2006 — conf
Power distribution techniques for dual VDD circuits.
ASP-DAC
Sarvesh H. Kulkarni, Dennis Sylvester
2004 A conf
A new algorithm for improved VDD assignment in low power dual VDD systems.
ISLPED
Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester
2004 J jnl
High performance level conversion for dual V
IEEE Trans. Very Large Scale Integr. Syst.
Sarvesh H. Kulkarni, Dennis Sylvester
2003 — conf
An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.
ISVLSI
Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw
2003 A* conf
Pushing ASIC performance in a power envelope.
DAC
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni