Sarvesh Bhardwaj

30 papers A* 5A 5Misc 5Journal 10Unranked 5

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ankur Sharma, David G. Chinnery, Tiago Reimann, Sarvesh Bhardwaj, Chris Chu
2015	A	`conf`	Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. ICCAD Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu
2014	A*	`conf`	On Timing Closure: Buffer Insertion for Hold-Violation Removal. DAC Pei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe
2010	J	`jnl`	Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. IEEE Trans. Very Large Scale Integr. Syst. Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2010	J	`jnl`	The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. Very Large Scale Integr. Syst. Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
2009	J	`jnl`	Secure and Robust Localization in a Wireless Ad Hoc Environment. IEEE Trans. Veh. Technol. Satyajayant Misra, Guoliang Xue, Sarvesh Bhardwaj
2008	J	`jnl`	A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel
2008	J	`jnl`	Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2008	J	`jnl`	Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. J. Low Power Electron. Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2008	Misc	`conf`	Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2008	J	`jnl`	Scalable model for predicting the effect of negative bias temperature instability for reliable design. IET Circuits Devices Syst. Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
2008	Misc	`conf`	Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2007	Misc	`conf`	A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. VLSI Design Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2007	—	`conf`	Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. PATMOS Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
2007	A*	`conf`	The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
2007	Misc	`conf`	Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. VLSI Design Sarma B. K. Vrudhula, Sarvesh Bhardwaj
2006	A	`conf`	A framework for statistical timing analysis using non-linear delay and slew models. ICCAD Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
2006	—	`conf`	LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. ISQED Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2006	A*	`conf`	Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. DAC Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao
2006	—	`conf`	Predictive Modeling of the NBTI Effect for Reliable Design. CICC Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
2006	J	`jnl`	Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electron. Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2006	—	`conf`	Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. ASP-DAC Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2006	A*	`conf`	Stochastic variational analysis of large power grids considering intra-die correlations. DAC Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
2005	—	`conf`	An efficient combinationality check technique for the synthesis of cyclic combinational circuits. ASP-DAC Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang
2005	A	`conf`	Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. ICCAD Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2005	A*	`conf`	Leakage minimization of nano-scale circuits in the presence of systematic and random variations. DAC Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2005	J	`jnl`	Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
2004	Misc	`conf`	Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj
2003	A	`conf`	AU: Timing Analysis Under Uncertainty. ICCAD Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
2002	A	`conf`	Estimation of signal arrival times in the presence of delay noise. ICCAD Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw