Sartaj K. Sahni

21 papers A 2C 2Misc 1Journal 14Unranked 2
YearRankTypeTitle / Venue / Authors
2022 J jnl
Algorithms for optimal min hop and foremost paths in interval temporal graphs.
Appl. Netw. Sci.
Anuj Jain, Sartaj K. Sahni
2021 J jnl
Announcement.
Int. J. Found. Comput. Sci.
Oscar H. Ibarra, Sartaj K. Sahni
2016 J jnl
Announcement.
Int. J. Found. Comput. Sci.
Francis Y. L. Chin, Oscar H. Ibarra, Sartaj K. Sahni
2013 — conf
Dynamic multistatic synthetic aperture radar (DMSAR) with image reconstruction algorithms and analysis.
AIPR
Guna Seetharaman, Eric T. Hayden, Mark S. Schmalz, William Chapman, Sanjay Ranka, Sartaj K. Sahni
2005 J jnl
Packet classification consuming small amount of memory.
IEEE/ACM Trans. Netw.
Xuehong Sun, Sartaj K. Sahni, Yiqiang Q. Zhao
2005 J jnl
Prefix and Interval-Partitioned Dynamic IP Router-Tables.
IEEE Trans. Computers
Haibin Lu, Kun Suk Kim, Sartaj K. Sahni
2004 C conf
A B-tree dynamic router-table design.
ISCC
Haibin Lu, Sartaj K. Sahni
2004 C conf
Dynamic IP router-tables using highest-priority matching.
ISCC
Haibin Lu, Sartaj K. Sahni
2004 — conf
Fast Update Algorithm for IP Forwarding Table Using Independent Sets.
HSNMC
Xuehong Sun, Sartaj K. Sahni, Yiqiang Q. Zhao
2001 J jnl
A Fast Algorithm for Transistor Folding.
VLSI Design
Edward Y. C. Cheng, Sartaj K. Sahni
1997 J jnl
Models, techniques, and algorithms for finding, selecting, and displaying patterns in strings and other discrete objects.
J. Syst. Softw.
Dinesh P. Mehta, Sartaj K. Sahni
1996 J jnl
Efficient net extraction for restricted orientation designs [VLSI layout].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mario Alberto López, Ravi Janardan, Sartaj K. Sahni
1995 Misc conf
A fast algorithm to test planar topological routability.
VLSI Design
Andrew Lim, Sartaj K. Sahni, Venkat Thanvantri
1994 A conf
Folding a stack of equal width components.
ICCAD
Venkat Thanvantri, Sartaj K. Sahni
1993 A conf
A fast algorithm for VLSI net extraction.
ICCAD
Mario Alberto López, Ravi Janardan, Sartaj K. Sahni
1989 J jnl
On path selection in combinational logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wing Ning Li, Sudhakar M. Reddy, Sartaj K. Sahni
1988 J jnl
Fast algorithm for polygon decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Surendra Nahar, Sartaj K. Sahni
1988 J jnl
Two NP-hard interchangeable terminal problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sartaj K. Sahni, San-Yuan Wu
1987 J jnl
A Systolic Design-Rule Checker.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rajiv Kane, Sartaj K. Sahni
1987 J jnl
Layering Algorithms For Single-Row Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
SangYong Han, Sartaj K. Sahni
1986 J jnl
VLSI Architectures for the Finite Impulse Response Filter.
IEEE J. Sel. Areas Commun.
Kam Cheng, Sartaj K. Sahni