Saroja V. Siddamal

14 papers Misc 4Journal 3Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
RISC-V Based SoC Design Featuring Fixed and Floating Point Units with Integrated FFT Accelerator for DSP Workloads.
HiPCW
Umer Kudachi, Saroja V. Siddamal, Shreevatsa Alawandi, Aishwarya Beedanal
2024 J jnl
2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues.
Integr.
Dharmaray Nedalgi, Saroja V. Siddamal, S. S. Kerur
2023 Misc conf
Supply Noise and Peak Current Reduction in High-Speed Output Drivers.
VLSID
Dharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal
2022 J jnl
Differential receiver with 2 × VDD input signals using 1 × VDD devices.
Integr.
Dharmaray Nedalgi, Saroja V. Siddamal
2022 J jnl
Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability.
J. Circuits Syst. Comput.
Dharmaray Nedalgi, Saroja V. Siddamal
2021 — conf
$2 \times \text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability.
APCCAS
Dharmaray Nedalgi, Saroja V. Siddamal
2021 Misc conf
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone.
VLSID
Dharmaray Nedalgi, Saroja V. Siddamal
2021 — conf
Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer.
APCCAS
Dharmaray Nedalgi, Saroja V. Siddamal
2020 — conf
Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator.
VDAT
Mandakini Kadam, Saroja V. Siddamal, Shripadraj Annigeri
2019 — conf
Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology.
VDAT
Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer
2019 Misc conf
Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter.
VLSID
Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. Siddamal, Sujata S. Kotabagi, Nalini C. Iyer
2018 — conf
Development of Data Acquisition System using non-invasive Hardware and 3D software for Electric all terrain Vehicle.
ICACCI
Akashaykumar H. Sunagar, Saroja V. Siddamal
2014 Misc conf
Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology.
VLSID
Narayan V. Sugur, Saroja V. Siddamal, Samba Sivam Vemala
2008 — conf
Design of High-Speed Floating Point Multiplier.
DELTA
Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga