Sarma Sastry

19 papers A* 7B 1C 1Misc 1Journal 7Unranked 2
YearRankTypeTitle / Venue / Authors
1993 J jnl
Probabilistic characterization of controllability in general homogeneous circuits.
Comput. Aided Des.
Amitava Majumdar, Sarma Sastry
1993 Misc conf
Statistical Analysis of Controllability.
VLSI Design
Amitava Majumdar, Sarma Sastry
1992 C conf
Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification.
ICCD
Yung-Te Lai, Sarma Sastry, Massoud Pedram
1992 A* conf
Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification.
DAC
Yung-Te Lai, Sarma Sastry
1992 A* conf
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits.
DAC
Amitava Majumdar, Sarma Sastry
1991 A* conf
A Branching Process Model for Observability Analysis of Combinational Circuits.
DAC
Sarma Sastry, Amitava Majumdar
1991 J jnl
Estimating the minimum of partitioning and floorplanning problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarma Sastry, Jen-I Pi
1991 A* conf
Flexible Transistor Matrix (FTM).
DAC
King C. Ho, Sarma Sastry
1991 J jnl
Test efficiency analysis of random self-test of sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarma Sastry, Amitava Majumdar
1991 — conf
Topological via minimization and routing.
Great Lakes Symposium on VLSI
Ahsan Abdullah, Sarma Sastry
1991 J jnl
VYUHA: A detailed router for multiple routing models.
Integr.
C. P. Ravikumar, Sarma Sastry
1989 J jnl
A hardware accelerator for hierarchical VLSI routing.
Integr.
C. P. Ravikumar, Sarma Sastry
1989 A* conf
An Investigation into Statistical Properties of Partitioning and Floorplanning Problems.
DAC
Sarma Sastry, Jen-I Pi
1989 — conf
Parallel Placement on Hypercube Architecture.
ICPP (3)
C. P. Ravikumar, Sarma Sastry
1988 J jnl
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarma Sastry, Melvin A. Breuer
1988 A* conf
Parallel Placement on Reduced Array Architecture.
DAC
C. P. Ravikumar, Sarma Sastry
1987 B conf
A General Purpose VLSI Array for Efficient Signal and Image Processsing.
ICPP
Viktor K. Prasanna, Sarma Sastry
1986 J jnl
Stochastic Models for Wireability Analysis of Gate Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarma Sastry, Alice C. Parker
1984 A* conf
On the relation between wire length distributions and placement of logic on master slice ICs.
DAC
Sarma Sastry, Alice C. Parker