Sarma B. K. Vrudhula

201 papers A* 24A 39B 7C 15Misc 11Journal 72Unranked 33

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Energy-Efficient, Delay-Constrained Edge Computing of a Network of DNNs. IEEE Trans. Computers Mehdi Ghasemi, Soroush Heidari, Young Geun Kim, Carole-Jean Wu, Sarma B. K. Vrudhula
2024	—	`conf`	A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers. ACM Great Lakes Symposium on VLSI Gian Singh, Sarma B. K. Vrudhula
2024	C	`conf`	A High Throughput, Energy-Efficient Architecture for Variable Precision Computing in DRAM. VLSI-SoC Gian Singh, Ayushi Dube, Sarma B. K. Vrudhula
2024	J	`jnl`	A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors. IEEE Trans. Circuits Syst. I Regul. Pap. Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
2024	J	`jnl`	An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2024	A*	`conf`	ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. HPCA Chetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria
2024	Misc	`conf`	Elastic Execution of Multi-Tenant DNNs on Heterogeneous Edge MPSoCs. SEC Soroush Heidari, Mehdi Ghasemi, Young Geun Kim, Carole-Jean Wu, Sarma B. K. Vrudhula
2024	—	`conf`	Energy-Efficient and Low-Latency Computation of Transcendental Functions in a Precision-Tunable PIM Architecture. ISVLSI Gian Singh, Ayushi Dube, Sarma B. K. Vrudhula
2024	A	`conf`	Hardware-Software Co-Design for Path Planning by Drones. IROS Ayushi Dube, Omkar Patil, Gian Singh, Nakul Gopalan, Sarma B. K. Vrudhula
2024	—	`conf`	HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. MLSys Gyudong Kim, Mehdi Ghasemi, Soroush Heidari, Seungryong Kim, Young Geun Kim, Sarma B. K. Vrudhula, Carole-Jean Wu
2024	J	`jnl`	HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. CoRR Gyudong Kim, Mehdi Ghasemi, Soroush Heidari, Seungryong Kim, Young Geun Kim, Sarma B. K. Vrudhula, Carole-Jean Wu
2023	J	`jnl`	A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula
2023	—	`conf`	A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. ISQED Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
2023	Misc	`conf`	PARAG: PIM Architecture for Real-Time Acceleration of GCNs. HiPC Gian Singh, Sanmukh R. Kuppannagari, Sarma B. K. Vrudhula
2023	J	`jnl`	Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems. CoRR Vidya A. Chhabria, Chetan Choppali Sudarshan, Sarma B. K. Vrudhula, Sachin S. Sapatnekar
2022	A	`conf`	A Flash-based Current-mode IC to Realize Quantized Neural Networks. DATE Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
2022	J	`jnl`	A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. IEEE Trans. Circuits Syst. I Regul. Pap. Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2022	J	`jnl`	A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells. CoRR Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
2022	J	`jnl`	CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs. IEEE Trans. Computers Soroush Heidari, Mehdi Ghasemi, Young Geun Kim, Carole-Jean Wu, Sarma B. K. Vrudhula
2022	J	`jnl`	EdgeWise: Energy-efficient CNN Computation on Edge Devices under Stochastic Communication Delays. ACM Trans. Embed. Comput. Syst. Mehdi Ghasemi, Daler N. Rakhmatov, Carole-Jean Wu, Sarma B. K. Vrudhula
2022	J	`jnl`	Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ankit Wagle, Sarma B. K. Vrudhula
2022	A	`conf`	Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons. ICCAD Ayushi Dube, Ankit Wagle, Gian Singh, Sarma B. K. Vrudhula
2021	J	`jnl`	A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. CoRR Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2021	C	`conf`	CIDAN: Computing in DRAM with Artificial Neurons. ICCD Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri
2021	J	`jnl`	CIDAN: Computing in DRAM with Artificial Neurons. CoRR Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri
2021	B	`conf`	Energy-Efficient Mapping for a Network of DNN Models at the Edge. SMARTCOMP Mehdi Ghasemi, Soroush Heidari, Young Geun Kim, Aaron Lamb, Carole-Jean Wu, Sarma B. K. Vrudhula
2020	C	`conf`	A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. ICCD Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2020	—	`conf`	A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron. ISQED Elham Azari, Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
2020	J	`jnl`	Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2020	J	`jnl`	ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. ACM Trans. Embed. Comput. Syst. Elham Azari, Sarma B. K. Vrudhula
2020	—	`conf`	Enabling Incremental Knowledge Transfer for Object Detection at the Edge. CVPR Workshops Mohammad Farhadi, Mehdi Ghasemi, Sarma B. K. Vrudhula, Yezhou Yang
2020	J	`jnl`	Enabling Incremental Knowledge Transfer for Object Detection at the Edge. CoRR Mohammad Farhadi Bajestani, Mehdi Ghasemi, Sarma B. K. Vrudhula, Yezhou Yang
2020	J	`jnl`	Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2019	A	`conf`	An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing. FPGA Elham Azari, Aykut Dengi, Sarma B. K. Vrudhula
2019	—	`conf`	An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing. IEEE BigData Elham Azari, Sarma B. K. Vrudhula
2019	J	`jnl`	ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. CoRR Elham Azari, Sarma B. K. Vrudhula
2019	A	`conf`	Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance. ICCAD Ankit Wagle, Elham Azari, Sarma B. K. Vrudhula
2019	J	`jnl`	Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties. IEEE Trans. Mob. Comput. Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula
2019	C	`conf`	Threshold Logic in a Flash. ICCD Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula
2019	J	`jnl`	Threshold Logic in a Flash. CoRR Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula
2018	J	`jnl`	ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018	A	`conf`	Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2018	B	`conf`	DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference. ISPASS Davesh Shingari, Akhil Arunkumar, Benjamin Gaudette, Sarma B. K. Vrudhula, Carole-Jean Wu
2018	J	`jnl`	Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic. IEEE Trans. Very Large Scale Integr. Syst. Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
2018	B	`conf`	FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area. FPL Ankit Wagle, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
2018	J	`jnl`	Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	A*	`conf`	A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. DAC Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula
2017	B	`conf`	An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	C	`conf`	End-to-end scalable FPGA accelerator for deep residual networks. ISCAS Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	A	`conf`	Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
2017	—	`conf`	Statistical library characterization using arbitrary polynomial chaos. LASCAS Mehmet Ince, Sule Ozev, Sarma B. K. Vrudhula
2016	C	`conf`	Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons. ISCAS Debayan Mahalanabis, M. Sivaraj, W. Chen, S. Shah, Hugh J. Barnaby, Michael N. Kozicki, Jennifer Blain Christen, Sarma B. K. Vrudhula
2016	J	`jnl`	Digital IP Protection Using Threshold Voltage Control. CoRR Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
2016	—	`conf`	Digital IP protection using threshold voltage control. ISQED Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
2016	J	`jnl`	Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks. CoRR Niranjan Kulkarni, Sarma B. K. Vrudhula
2016	C	`conf`	High-performance face detection with CPU-FPGA acceleration. ISCAS Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2016	A*	`conf`	Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee. HPCA Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula
2016	J	`jnl`	Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula
2016	B	`conf`	Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2016	A	`conf`	Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
2015	J	`jnl`	A Nonvolatile Sense Amplifier Flip-Flop Using Programmable Metallization Cells. IEEE J. Emerg. Sel. Topics Circuits Syst. Debayan Mahalanabis, Vineeth Bharadwaj, Hugh J. Barnaby, Sarma B. K. Vrudhula, Michael N. Kozicki
2015	C	`conf`	Design of threshold logic gates using emerging devices. ISCAS Sarma B. K. Vrudhula, Niranjan Kulkarni, Jinghua Yang
2015	—	`conf`	Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. CICC Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula
2015	C	`conf`	Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. ICCD Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
2015	C	`conf`	Fast and robust differential flipflops and their extension to multi-input threshold gates. ISCAS Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma B. K. Vrudhula
2015	A	`conf`	Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2015	J	`jnl`	Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2015	A	`conf`	Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2015	J	`jnl`	Thermal aware floorplanning incorporating temperature dependent wire delay estimation. Microprocess. Microsystems Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula
2014	—	`conf`	A fast, energy efficient, field programmable threshold-logic array. FPT Niranjan Kulkarni, Jinghua Yang, Sarma B. K. Vrudhula
2014	A*	`conf`	Branch-Aware Loop Mapping on CGRAs. DAC Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
2014	J	`jnl`	Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling. IEEE Trans. Computers Vinay Hanumaiah, Sarma B. K. Vrudhula
2014	—	`conf`	Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. NANOARCH Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula
2014	J	`jnl`	Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks. ACM Trans. Sens. Networks Benjamin Gaudette, Vinay Hanumaiah, Marwan Krunz, Sarma B. K. Vrudhula
2014	—	`conf`	Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2014	—	`conf`	Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao
2014	J	`jnl`	STEAM: A Smart Temperature and Energy Aware Multicore Controller. ACM Trans. Embed. Comput. Syst. Vinay Hanumaiah, Digant Desai, Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula
2014	J	`jnl`	Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. J. Parallel Distributed Comput. Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula
2014	J	`jnl`	The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits. Fundam. Informaticae Zihan Xu, Matteo Cavaliere, Pei An, Sarma B. K. Vrudhula, Yu Cao
2013	A*	`conf`	REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs). DAC Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
2012	A*	`conf`	EPIMap: using epimorphism to map applications on CGRAs. DAC Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
2012	A	`conf`	Minimizing area and power of sequential CMOS circuits using threshold decomposition. ICCAD Niranjan Kulkarni, Nishant Nukala, Sarma B. K. Vrudhula
2012	A*	`conf`	Optimal range assignment in solar powered active wireless sensor networks. INFOCOM Benjamin Gaudette, Vinay Hanumaiah, Sarma B. K. Vrudhula, Marwan Krunz
2012	—	`conf`	Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture. NANOARCH Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula
2012	J	`jnl`	Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors. IEEE Trans. Computers Vinay Hanumaiah, Sarma B. K. Vrudhula
2011	—	`conf`	A new balanced 4-moduli set {2 ACM Great Lakes Symposium on VLSI Gayathri Chalivendra, Vinay Hanumaiah, Sarma B. K. Vrudhula
2011	B	`conf`	Enabling Multithreading on CGRAs. ICPP Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula
2011	J	`jnl`	Identification of Threshold Functions and Synthesis of Threshold Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski
2011	J	`jnl`	Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
2011	A	`conf`	Reliability-aware thermal management for hard real-time applications on multi-core processors. DATE Vinay Hanumaiah, Sarma B. K. Vrudhula
2011	—	`conf`	Temperature dependent wire delay estimation in floorplanning. NORCHIP Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula
2010	—	`conf`	A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. ISVLSI Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula
2010	J	`jnl`	Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. IEEE Trans. Very Large Scale Integr. Syst. Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2010	J	`jnl`	The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. Very Large Scale Integr. Syst. Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
2009	Misc	`conf`	A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula
2009	J	`jnl`	Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ravishankar Rao, Sarma B. K. Vrudhula
2009	A	`conf`	Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. ICCAD Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
2009	J	`jnl`	Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids. IEEE Trans. Very Large Scale Integr. Syst. Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang, Sarma B. K. Vrudhula
2009	A	`conf`	Performance optimal speed control of multi-core processors under thermal constraints. DATE Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
2009	A*	`conf`	Throughput optimal task allocation under thermal constraints for multi-core processors. DAC Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha
2008	—	`conf`	A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. ISQED Saravanan Ramamoorthy, Haibo Wang, Sarma B. K. Vrudhula
2008	—	`conf`	A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. ISQED Amit Goel, Sarma B. K. Vrudhula, Feroze Taraporevala, Praveen Ghanta
2008	J	`jnl`	A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel
2008	J	`jnl`	A fuel-cell-battery hybrid for portable embedded systems. ACM Trans. Design Autom. Electr. Syst. Kyungsoo Lee, Naehyuck Chang, Jianli Zhuo, Chaitali Chakrabarti, Sudheendra Kadri, Sarma B. K. Vrudhula
2008	A	`conf`	Analytical results for design space exploration of multi-core processors employing thread migration. ISLPED Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski
2008	A	`conf`	Current source based standard cell model for accurate signal integrity and timing analysis. DATE Amit Goel, Sarma B. K. Vrudhula
2008	—	`conf`	Decomposition based approach for synthesis of multi-level threshold logic circuits. ASP-DAC Tejaswi Gowda, Sarma B. K. Vrudhula
2008	A	`conf`	Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. ICCAD Ravishankar Rao, Sarma B. K. Vrudhula
2008	J	`jnl`	Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2008	J	`jnl`	Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. J. Low Power Electron. Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2008	Misc	`conf`	Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2008	J	`jnl`	Scalable model for predicting the effect of negative bias temperature instability for reliable design. IET Circuits Devices Syst. Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
2008	A*	`conf`	Statistical waveform and current source based standard cell models for accurate timing analysis. DAC Amit Goel, Sarma B. K. Vrudhula
2008	Misc	`conf`	Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2008	—	`conf`	Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila. BIODEVICES (1) Tejaswi Gowda, Samuel Leshner, Sarma B. K. Vrudhula, Seungchan Kim
2007	Misc	`conf`	A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. VLSI Design Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2007	J	`jnl`	Analysis of Power Supply Noise in the Presence of Process Variations. IEEE Des. Test Comput. Praveen Ghanta, Sarma B. K. Vrudhula
2007	—	`conf`	Combinational equivalence checking for threshold logic circuits. ACM Great Lakes Symposium on VLSI Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod
2007	—	`conf`	Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. PATMOS Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
2007	J	`jnl`	Energy optimal speed control of a producer-consumer device pair. ACM Trans. Embed. Comput. Syst. Ravishankar Rao, Sarma B. K. Vrudhula
2007	—	`conf`	Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. ISMVL Krzysztof S. Berezowski, Sarma B. K. Vrudhula
2007	J	`jnl`	Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. J. Multiple Valued Log. Soft Comput. Krzysztof S. Berezowski, Sarma B. K. Vrudhula
2007	Misc	`conf`	Performance optimal processor throttling under thermal constraints. CASES Ravishankar Rao, Sarma B. K. Vrudhula
2007	J	`jnl`	Stochastic Power Grid Analysis Considering Process Variations CoRR Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
2007	—	`conf`	Synthesis of threshold logic circuits using tree matching. ECCTD Tejaswi Gowda, Samuel Leshner, Sarma B. K. Vrudhula, Goran Konjevod
2007	A*	`conf`	The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
2007	A	`conf`	Throughput of multi-core processors under thermal constraints. ISLPED Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti
2007	Misc	`conf`	Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. VLSI Design Sarma B. K. Vrudhula, Sarvesh Bhardwaj
2006	A	`conf`	A framework for statistical timing analysis using non-linear delay and slew models. ICCAD Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
2006	A	`conf`	An optimal analytical solution for processor speed control with thermal constraints. ISLPED Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang
2006	J	`jnl`	Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kaviraj Chopra, Sarma B. K. Vrudhula
2006	J	`jnl`	Energy-Optimal Speed Control of a Generic Device. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ravishankar Rao, Sarma B. K. Vrudhula
2006	A*	`conf`	Extending the lifetime of fuel cell based hybrid systems. DAC Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula
2006	J	`jnl`	Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta
2006	A*	`conf`	High-level power management of embedded systems with application-specific energy cost functions. DAC Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula
2006	J	`jnl`	Joint Optimization of Transmit Power-Time and Bit Energy Efficiency in CDMA Wireless Sensor Networks. IEEE Trans. Wirel. Commun. Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula
2006	—	`conf`	LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. ISQED Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2006	A	`conf`	Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. ISLPED Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula
2006	A*	`conf`	Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. DAC Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao
2006	—	`conf`	Predictive Modeling of the NBTI Effect for Reliable Design. CICC Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
2006	J	`jnl`	Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electron. Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2006	—	`conf`	Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. ASP-DAC Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
2006	A*	`conf`	Stochastic variational analysis of large power grids considering intra-die correlations. DAC Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
2006	—	`conf`	Variational Interconnect Delay Metrics for Statistical Timing Analysis. ISQED Praveen Ghanta, Sarma B. K. Vrudhula
2005	C	`conf`	Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. DSD Krzysztof S. Berezowski, Sarma B. K. Vrudhula
2005	A	`conf`	Battery optimization vs energy optimization: which to choose and when? ICCAD Ravishankar Rao, Sarma B. K. Vrudhula
2005	A*	`conf`	Energy optimal speed control of devices with discrete speed sets. DAC Ravishankar Rao, Sarma B. K. Vrudhula
2005	A	`conf`	Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. ICCAD Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2005	A*	`conf`	Leakage minimization of nano-scale circuits in the presence of systematic and random variations. DAC Sarvesh Bhardwaj, Sarma B. K. Vrudhula
2005	B	`conf`	Power balanced coverage-time optimization for clustered wireless sensor networks. MobiHoc Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula
2005	J	`jnl`	Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
2005	A	`conf`	Stochastic Power Grid Analysis Considering Process Variations. DATE Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
2004	A	`conf`	A Framework for Battery-Aware Sensor Management. DATE Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan
2004	A*	`conf`	A methodology to improve timing yield in the presence of process variations. DAC Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang
2004	Misc	`conf`	Disk drive energy optimization for audio-video applications. CASES Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan
2004	Misc	`conf`	Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj
2004	Misc	`conf`	Energy Profiler for Hardware/Software Co-Design. VLSI Design Raghukiran Sreeramaneni, Sarma B. K. Vrudhula
2004	A	`conf`	Energy optimization for a two-device data flow chain. ICCAD Ravishankar Rao, Sarma B. K. Vrudhula
2004	A*	`conf`	Implicit pseudo boolean enumeration algorithms for input vector control. DAC Kaviraj Chopra, Sarma B. K. Vrudhula
2004	A	`conf`	Stochastic analysis of interconnect performance in the presence of process variations. ICCAD Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula
2004	A*	`conf`	Variational delay metrics for interconnect timing analysis. DAC Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
2003	J	`jnl`	A model for battery lifetime analysis for organizing applications on a pocket computer. IEEE Trans. Very Large Scale Integr. Syst. Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach
2003	A	`conf`	AU: Timing Analysis Under Uncertainty. ICCAD Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
2003	A	`conf`	Analysis of discharge techniques for multiple battery systems. ISLPED Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov
2003	J	`jnl`	Battery Modeling for Energy-Aware System Design. Computer Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov
2003	A*	`conf`	Computation and Refinement of Statistical Bounds on Circuit Delay. DAC Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
2003	J	`jnl`	Energy management for battery-powered embedded systems. ACM Trans. Embed. Comput. Syst. Daler N. Rakhmatov, Sarma B. K. Vrudhula
2003	J	`jnl`	Probabilistic analysis of interconnect coupling noise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul
2003	A	`conf`	Statistical Timing Analysis Using Bounds. DATE Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
2002	J	`jnl`	Algorithms for minimizing standby power in deep submicrometer, dual-V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qi Wang, Sarma B. K. Vrudhula
2002	A	`conf`	Battery lifetime prediction for energy-aware computing. ISLPED Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach
2002	A*	`conf`	Battery-conscious task sequencing for portable devices including voltage/clock scaling. DAC Daler N. Rakhmatov, Sarma B. K. Vrudhula, Chaitali Chakrabarti
2002	J	`jnl`	Behavioral synthesis of field programmable analog array circuits. ACM Trans. Design Autom. Electr. Syst. Haibo Wang, Sarma B. K. Vrudhula
2002	A	`conf`	Estimation of signal arrival times in the presence of delay noise. ICCAD Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
2002	A*	`conf`	Estimation of the likelihood of capacitive coupling noise. DAC Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul
2002	—	`conf`	Hardware-software bipartitioning for dynamically reconfigurable systems. CODES Daler N. Rakhmatov, Sarma B. K. Vrudhula
2002	—	`conf`	Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
2002	—	`conf`	Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula
2001	A	`conf`	An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. ICCAD Daler N. Rakhmatov, Sarma B. K. Vrudhula
2001	A	`conf`	Minimizing routing configuration cost in dynamically reconfigurable FPGAs. IPDPS Daler N. Rakhmatov, Sarma B. K. Vrudhula
2001	A	`conf`	Time-to-failure estimation for batteries in portable electronic systems. ISLPED Daler N. Rakhmatov, Sarma B. K. Vrudhula
2000	J	`jnl`	Adaptive Multiuser Online Reconfigurable Engine. IEEE Des. Test Comput. Daler N. Rakhmatov, Sarma B. K. Vrudhula, Thomas J. Brown, Ajay Nagarandal
1999	C	`conf`	An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. ICCD Qi Wang, Sarma B. K. Vrudhula
1999	J	`jnl`	Power reduction and power-delay trade-offs using logic transformations. ACM Trans. Design Autom. Electr. Syst. Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly
1998	J	`jnl`	A Technique for Estimating Signal Activity in Logic Circuits. Integr. Comput. Aided Eng. Hong-Yu Xie, Sarma B. K. Vrudhula
1998	A	`conf`	Data Driven Power Optimization of Sequential Circuits. DATE Qi Wang, Sarma B. K. Vrudhula
1998	C	`conf`	On short circuit power estimation of CMOS inverters. ICCD Qi Wang, Sarma B. K. Vrudhula
1998	A	`conf`	Static power optimization of deep submicron CMOS circuits for dual VT technology. ICCAD Qi Wang, Sarma B. K. Vrudhula
1997	A*	`conf`	An Investigation of Power Delay Trade-Offs on PowerPC Circuits. DAC Qi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly
1997	C	`conf`	Macro-instruction generation for dynamic logic caching. IEEE International Workshop on Rapid System Prototyping K. McCarley, Sarma B. K. Vrudhula
1997	C	`conf`	Rapid prototyping of networks of asynchronous multiple functional units. IEEE International Workshop on Rapid System Prototyping E. Tsun, Sarma B. K. Vrudhula
1996	J	`jnl`	Formal Verification Using Edge-Valued Binary Decision Diagrams. IEEE Trans. Computers Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
1996	A	`conf`	Multi-level logic optimization for low power using local logic transformations. ICCAD Qi Wang, Sarma B. K. Vrudhula
1995	J	`jnl`	Fault Coverage and Test Length Estimation for Random Pattern Testing. IEEE Trans. Computers Amitava Majumdar, Sarma B. K. Vrudhula
1994	J	`jnl`	EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
1994	J	`jnl`	Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. King C. Ho, Sarma B. K. Vrudhula
1994	J	`jnl`	Techniques for estimating test length under random test. J. Electron. Test. Amitava Majumdar, Sarma B. K. Vrudhula
1993	J	`jnl`	A design of a fast and area efficient multi-input Muller C-element. IEEE Trans. Very Large Scale Integr. Syst. T.-Y. Wuu, Sarma B. K. Vrudhula
1993	J	`jnl`	Analysis of signal probability in logic circuits using stochastic models. IEEE Trans. Very Large Scale Integr. Syst. Amitava Majumdar, Sarma B. K. Vrudhula
1993	A*	`conf`	BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis. DAC Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
1993	A	`conf`	FGILP: an integer linear program solver based on function graphs. ICCAD Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula