Sarath Mohanachandran Nair

18 papers A 6B 1C 1Misc 2Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2020 A conf
A Universal Spintronic Technology based on Multifunctional Standardized Stack.
DATE
Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory di Pendina, Guillaume Prenat
2020 B conf
Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory.
ETS
Sarath Mohanachandran Nair, Christopher Münch, Mehdi Baradaran Tahoori
2020 A conf
Dynamic Faults based Hardware Trojan Design in STT-MRAM.
DATE
Sarath Mohanachandran Nair, Rajendra Bishnoi, Arunkumar Vijayan, Mehdi Baradaran Tahoori
2020 Misc conf
Mitigating Read Failures in STT-MRAM.
VTS
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2020 — conf
Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
IRPS
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi B. Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor
2020 Misc conf
Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.
VTS
Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui
2020 — —
Variation Analysis, Fault Modeling and Yield Improvement of Emerging Spintronic Memories
Sarath Mohanachandran Nair
2019 J jnl
A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2019 J jnl
A Spintronics Memory PUF for Resilience Against Cloning Counterfeit.
IEEE Trans. Very Large Scale Integr. Syst.
Samir Ben Dodo, Rajendra Bishnoi, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori
2019 — conf
Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
IRPS
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor
2019 C conf
Variation-aware Fault Modeling and Test Generation for STT-MRAM.
IOLTS
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Hayk T. Grigoryan, Grigor Tshagharyan
2018 A conf
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.
ITC
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian
2018 A conf
Parametric failure modeling and yield analysis for STT-MRAM.
DATE
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018 — conf
Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM.
ASP-DAC
Nour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018 A conf
Using multifunctional standardized stack as universal spintronic technology for IoT.
DATE
Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frederic Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat
2018 J jnl
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori
2017 — conf
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.
ISVLSI
Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat
2017 A conf
VAET-STT: A variation aware estimator tool for STT-MRAM based memories.
DATE
Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori