Sarang Kazeminia

22 papers Journal 8Unranked 14

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	A low-jitter leakage-free digitally calibrated phase locked loop. Comput. Electr. Eng. Sarang Kazeminia, Arefeh Soltani
2019	J	`jnl`	A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs. Integr. Sarang Kazeminia
2018	J	`jnl`	A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs. Integr. Sarang Kazeminia, Khayrollah Hadidi
2017	—	`conf`	An extendable global clock high-speed binary counter compatible to the FPGA CLBs. MIXDES Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur
2016	—	`conf`	A 800MS/s, 150µV input-referred offset single-stage latched comparator. MIXDES Sarang Kazeminia, Sina Mahdavi
2016	—	`conf`	Bulk controlled offset cancellation mechanism for single-stage latched comparator. MIXDES Sarang Kazeminia, Sina Mahdavi, Reza Gholamnejad
2016	—	`conf`	Digitally-assisted gain calibration strategy for open-loop residue amplifiers in pipeline ADCs. APCCAS Sarang Kazeminia, Arefeh Soltani
2016	—	`conf`	Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs. MIXDES Sarang Kazeminia, Sina Mahdavi, Khayrollah Hadidi
2016	—	`conf`	Programmable incrementing/decrementing binary accumulator for high-speed calibration loops. ICECS Arefeh Soltani, Roozbeh Abdollahi, Sarang Kazeminia
2016	—	`conf`	Single-stage offset-cancelled latched comparator scheduled by multi-level control on reset switch. APCCAS Sarang Kazeminia, Arefeh Soltani
2015	J	`jnl`	A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump. J. Circuits Syst. Comput. Sarang Kazeminia, Sobhan Sofimowloodi, Khayrollah Hadidi
2015	J	`jnl`	A Wide-Range Low-Jitter PLL Based on Fast-Response VCO and Simplified Straightforward Methodology of Loop Stabilization in Integer-N PLLs. J. Circuits Syst. Comput. Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei
2015	—	`conf`	A digitally assisted 20MHz-600MHz 16-phase DLL enhanced with dynamic gain control loop. ECCTD Arash Hejazi, Sarang Kazeminia, Roozbeh Abdollahi
2013	—	`conf`	Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs. ECCTD Sarang Kazeminia, Obalit Shino, Ehsan Haghighi, Khayrollah Hadidi
2011	J	`jnl`	A 500 MS/s 600 µW 300 µm IEICE Trans. Electron. Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei
2011	—	`conf`	Effect of bandgap energy temperature dependence on thermal coefficient of bandgap reference voltage. ECCTD Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei, Mohammad-Naghi Azarmanesh
2010	—	`conf`	High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection. APCCAS Sarang Kazeminia, Morteza Mousazadeh, Khayrollah Hadidi, Abdollah Khoei
2009	—	`conf`	Design of high-speed high-precision voltage-mode MAX-MIN circuits with low area and low power consumption. ECCTD Mohammad Soleimani, Abdollah Khoei, Khayrollah Hadidi, Sarang Kazeminia
2008	J	`jnl`	A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sarang Kazeminia, Khayrollah Hadidi, Abdollah Khoei
2007	—	`conf`	An Open Loop Phase Shifter and Frequency Synthesizer. ICECS Sarang Kazeminia, Khayrollah Hadidi
2007	J	`jnl`	High Speed High Precision voltage-Mode Max and Min Circuits. J. Circuits Syst. Comput. Sarang Kazeminia, Abdollah Khoei, Khayrollah Hadidi
2006	—	`conf`	High Speed High Precision Voltage-Mode MAX and MIN Circuits. ICECS Sarang Kazeminia, Abdollah Khoei, Khayrollah Hadidi