Saptarsi Das

14 papers C 3Misc 2Journal 4Unranked 5
YearRankTypeTitle / Venue / Authors
2021 C conf
Transport Triggered near Memory Accelerator for Deep Learning.
ISCAS
Kavitha T. Madhu, Saptarsi Das, Abhishek Tyagi, Ankur Deshwal, Joonho Song, Seungwon Lee
2020 C conf
A Systolic Dataflow Based Accelerator for CNNs.
ISCAS
Saptarsi Das, Arnab Roy, Kiran Kolar Chandrasekharan, Ankur Deshwal, Sehwan Lee
2017 J jnl
Energy aware synthesis of application kernels through composition of data-paths on a CGRA.
Integr.
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
2016 — conf
Flexible resource allocation and management for application graphs on ReNÉ MPSoC.
PARMA-DITAM@HiPEAC
Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Madhava Krishna C., S. K. Nandy, Ranjani Narayan
2016 Misc conf
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.
VLSID
Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan
2015 — conf
Compiling HPC Kernels for the REDEFINE CGRA.
HPCC/CSS/ICESS
Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2015 — conf
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array.
iNIS
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
2014 J jnl
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths.
J. Syst. Archit.
Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan
2014 — conf
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath.
ICSAMOS
Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C., Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2011 C conf
A Method for Flexible Reduction over Binary Fields using a Field Multiplier.
SECRYPT
Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy
2011 — conf
Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields.
ICETE (Selected Papers)
Saptarsi Das, Ranjani Narayan, Soumitra Kumar Nandy
2011 J jnl
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.
IPSJ Trans. Syst. LSI Des. Methodol.
Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan
2009 J jnl
REDEFINE: Runtime reconfigurable polymorphic ASIC.
ACM Trans. Embed. Comput. Syst.
Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan
2009 Misc conf
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.
CASES
Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan