Sanu Mathew - RankMe

93 papers A* 3A 6C 6Misc 3Journal 16Unranked 59

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	HERACLES: 8192-Way SIMD Programmable Scalable Fully-Homomorphic Encryption SoC for Privacy-Preserving Cloud Computing in Intel 3 CMOS. ISSCC Anupam Golder, Raghavan Kumar, Sachin Taneja, Kylan Race, Paolo A. Aseron, James Greensky, Wen Wang, Huijing Gong, Lalith Kethareswaran, Vikram B. Suresh, Adish Vartak, AppaRao Challagundla, Jeremy Casas, Poornima Lalwaney, Duhyeong Kim, Christopher N. Gutierrez, Ernesto Zamora Ramos, Wonhee Cho, Jose M. Rojas Chaves, Michael Steiner, Dan Lake, Nataraj Yennampelli, Karthik Nivarthi, Kamalakanth Bijinapally, Bala Prasad Talamala, Sravanth Valluri, Vasantha Srirambhatla, Chris Wilkerson, Rosario Cammarota, Sanu Mathew
2025	—	`conf`	A 2455μm CICC Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew
2025	J	`jnl`	A 65-nm Delta-Sigma ADC-Based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor. IEEE Solid State Circuits Lett. Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury
2025	J	`jnl`	Writing a Good Security Paper for ISSCC (2025). CoRR Utsav Banerjee, Chiraag Juvekar, Yong Ki Lee, Leibo Liu, Sanu Mathew, Thomas Pöppelmann, Shreyas Sen, Takeshi Sugawara, Ingrid Verbauwhede, Rabia Tugce Yazicigil
2024	—	`conf`	A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS. VLSI Technology and Circuits Raghavan Kumar, Sachin Taneja, Vivek De, Sanu Mathew
2024	—	`conf`	A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω. VLSI Technology and Circuits Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury
2024	A*	`conf`	UFC: A Unified Accelerator for Fully Homomorphic Encryption. MICRO Minxuan Zhou, Yujin Nam, Xuan Wang, Youhak Lee, Chris Wilkerson, Raghavan Kumar, Sachin Taneja, Sanu Mathew, Rosario Cammarota, Tajana Rosing
2023	—	`conf`	218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS. VLSI Technology and Circuits Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew
2023	—	`conf`	A 100Gbps Fault-Injection Attack Resistant AES-256 Engine with 99.1-to-99.99% Error Coverage in Intel 4 CMOS. ISSCC Raghavan Kumar, Avinash Varna, Carlos Tokunaga, Sachin Taneja, Vivek De, Sanu Mathew
2022	—	`conf`	A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. VLSI Technology and Circuits Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew
2022	—	`conf`	Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC. ISSCC Vikram B. Suresh, Chandra S. Katta, Srinivasan Rajagopalan, Tao Z. Zhou, Amit Kumar Patel, Raju Rakha, Nikhil Krishna Gopalakrishna, Sanu Mathew, Ajat Hukkoo
2022	J	`jnl`	EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Debayan Das, Mayukh Nath, Baibhab Chatterjee, Raghavan Kumar, Xiaosen Liu, Harish Krishnamurthy, Manoj R. Sastry, Sanu Mathew, Santosh Ghosh, Shreyas Sen
2022	—	`conf`	Fine-Grained Electromagnetic Side-Channel Analysis Resilient Secure AES Core with Stacked Voltage Domains and Spatio-temporally Randomized Circuit Blocks. ESSCIRC Meizhi Wang, Sirish Oruganti, Shanshan Xie, Raghavan Kumar, Sanu Mathew, Jaydeep P. Kulkarni
2021	J	`jnl`	EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing. IEEE J. Solid State Circuits Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish K. Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2021	—	`conf`	Session 4 Overview: Processors Digital Architectures and Systems Subcommittee. ISSCC Sanu Mathew, Shidhartha Das, Hugh Mair
2020	—	`conf`	25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De
2020	—	`conf`	27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation. ISSCC Debayan Das, Josef Danial, Anupam Golder, Nirmoy Modak, Shovan Maity, Baibhab Chatterjee, Dong-Hyun Seo, Muya Chang, Avinash Varna, Harish Krishnamurthy, Sanu Mathew, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen
2020	—	`conf`	A 0.26% BER, 10 VLSI Circuits Vikram B. Suresh, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew
2020	—	`conf`	A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. VLSI Circuits Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew
2020	—	`conf`	A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. VLSI Circuits Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish Krishnamurthy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu Mathew
2020	A*	`conf`	INVITED: A 0.26% BER, Machine-Learning Resistant 10 DAC Vikram B. Suresh, Raghavan Kumar, Sanu Mathew
2020	—	`conf`	Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De
2019	—	`conf`	A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. VLSI Circuits Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator. ISSCC Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2019	—	`conf`	A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. CICC Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Kirk Yap, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew
2019	—	`conf`	A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. CICC Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew
2019	—	`conf`	A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. VLSI Circuits Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 4900×m VLSI Circuits Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
2019	—	`conf`	A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
2019	C	`conf`	Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators. ARITH Himanshu Kaul, Mark A. Anders, Sanu Mathew, Seongjong Kim, Ram Krishnamurthy
2018	—	`conf`	2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. VLSI Circuits Mark A. Anders, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2 VLSI Circuits Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. ESSCIRC Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Kam Krisnnamurthy
2018	—	`conf`	A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. ESSCIRC Vikram B. Suresh, Sudhir Satpathy, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. A-SSCC Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. VLSI Circuits Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De
2018	J	`jnl`	Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator. CoRR Monodeep Kar, Arvind Singh, Sanu Mathew, Santosh Ghosh, Anand Rajan, Vivek De, Raheem A. Beyah, Saibal Mukhopadhyay
2018	A	`conf`	Exploiting on-chip power management for side-channel security. DATE Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2018	—	`conf`	Keynote 1: The road to resilient computing in autonomous driving is paved with redundancy. IRPS Nirmal R. Saxena, Sanu Mathew, Krishna Saraswat
2018	—	`conf`	Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. A-SSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	A	`conf`	Ultra-low energy circuit building blocks for security technologies. DATE Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy
2017	—	`conf`	8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. ISSCC Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	—	`conf`	Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies. CICC Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram K. Krishnamurthy
2017	—	`conf`	Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering. ESSCIRC Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	A	`conf`	Invited paper: Low power requirements and side-channel protection of encryption engines: Challenges and opportunities. ISLPED Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	A	`conf`	Invited paper: Ultra-low energy security circuit primitives for IoT platforms. ISLPED Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy
2017	J	`jnl`	Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators. J. Hardw. Syst. Secur. Arvind Singh, Monodeep Kar, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2017	A	`conf`	Security keynote: Ultra-low-energy security circuit primitives for IoT platforms. ITC Sanu Mathew
2016	—	`conf`	250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. VLSI Circuits Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy
2016	—	`conf`	A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. A-SSCC Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Gregory K. Chen, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De
2016	—	`conf`	A 350mV-900mV 2.1GHz 0.011mm VLSI Circuits Amit Agarwal, Steven Hsu, Mark A. Anders, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy
2016	—	`conf`	A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. VLSI Circuits Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De
2016	A	`conf`	Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines. ISLPED Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay
2016	C	`conf`	Hardware Implementation of AES Using Area-Optimal Polynomials for Composite-Field Representation GF(2^4)^2 of GF(2^8). ARITH Shay Gueron, Sanu Mathew
2016	C	`conf`	Ultra-low energy security circuits for IoT applications. ICCD Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Ram Krishnamurthy
2015	J	`jnl`	340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy
2015	—	`conf`	μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. ESSCIRC Sanu Mathew, David Johnston, Paul Newman, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2014	—	`conf`	13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. ESSCIRC Sudhir Satpathy, Sanu Mathew, Jiangtao Li, Patrick Koeberl, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2014	—	`conf`	340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2 VLSIC Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2013	J	`jnl`	A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. IEEE J. Solid State Circuits Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar
2013	J	`jnl`	A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram K. Krishnamurthy
2013	Misc	`conf`	Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers. ACSSC Andrew Carter, Paula Ning, William Koven, David Money Harris, Michael Braly, Nathan Jones, Julien Massas, Trevin Murakami, Alexandra Simoni, Sanu Mathew
2013	C	`conf`	Split-Path Fused Floating Point Multiply Accumulate (FPMAC). IEEE Symposium on Computer Arithmetic Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy, Vasantha Erraguntla
2012	J	`jnl`	2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors. IEEE J. Solid State Circuits Sanu Mathew, Suresh Srinivasan, Mark A. Anders, Himanshu Kaul, Steven Hsu, Farhana Sheikh, Amit Agarwal, Sudhir Satpathy, Ram Krishnamurthy
2012	—	`conf`	A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS. ESSCIRC Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2012	—	`conf`	A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS. ISSCC Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2011	J	`jnl`	53 Gbps Native GF(2 IEEE J. Solid State Circuits Sanu Mathew, Farhana Sheikh, Michael E. Kounavis, Shay Gueron, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Ram Krishnamurthy
2011	—	`conf`	A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS. ESSCIRC Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2011	A*	`conf`	High-performance energy-efficient encryption in the sub-45nm CMOS Era. DAC Ram Krishnamurthy, Sanu Mathew, Farhana Sheikh
2010	—	`conf`	18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. ESSCIRC Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy
2010	—	`conf`	3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS. ESSCIRC Sanu Mathew, Michael E. Kounavis, Farhana Sheikh, Steven Hsu, Amit Agarwal, Himanshu Kaul, Mark A. Anders, Frank L. Berry, Ram Krishnamurthy
2010	J	`jnl`	A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE J. Solid State Circuits Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2009	—	`conf`	A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2009	Misc	`conf`	A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. VLSI Design Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy
2008	Misc	`conf`	A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. VLSI Design Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron
2008	—	`conf`	A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2007	—	`conf`	A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. ISSCC Mark A. Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2007	—	`conf`	A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS. SoCC Sanu Mathew, David Money Harris, Mark A. Anders, Steven Hsu, Ram Krishnamurthy
2006	—	`conf`	A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core. ISSCC Sapumal B. Wijeratne, Nanda Siddaiah, Sanu Mathew, Mark A. Anders, Ram Krishnamurthy, Jeremy Anderson, Seung Hwang, Matthew Ernest, Mark D. Nardin
2006	—	`conf`	An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. ISSCC Steven K. Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy, Shekhar Borkar
2005	—	`conf`	A 2GHz 13.6mW 12 × 9b multiplier for energy efficient FFT accelerators. ESSCIRC Steven Hsu, Vishak Venkatraman, Sanu Mathew, Himanshu Kaul, Mark A. Anders, Saurabh Dighe, Wayne P. Burleson, Ram Krishnamurthy
2005	C	`conf`	An Improved Unified Scalable Radix-2 Montgomery Multiplier. IEEE Symposium on Computer Arithmetic David Money Harris, Ram Krishnamurthy, Mark A. Anders, Sanu Mathew, Steven Hsu
2005	J	`jnl`	Comparison of high-performance VLSI adders in the energy-delay space. IEEE Trans. Very Large Scale Integr. Syst. Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
2003	J	`jnl`	A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core. IEEE J. Solid State Circuits Sanu Mathew, Mark A. Anders, Ram K. Krishnamurthy, Shekhar Borkar
2003	J	`jnl`	A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. IEEE J. Solid State Circuits Steven Hsu, Atila Alvandpour, Sanu Mathew, Shih-Lien Lu, Ram K. Krishnamurthy, Shekhar Borkar
2003	C	`conf`	Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. IEEE Symposium on Computer Arithmetic Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
2002	J	`jnl`	5-GHz 32-bit integer execution core in 130-nm dual-V IEEE J. Solid State Circuits Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar