Santosh Kumar Vishvakarma

104 papers C 2Misc 6Journal 66Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Adaptive-precision SIMD architecture for high-throughput and resource-efficient DNN acceleration. Integr. Vasundhara Trivedi, Harman Singh Bagga, Gopal Raut, Santosh Kumar Vishvakarma
2026	J	`jnl`	Bio-RV: Low-Power Resource-Efficient RISC-V Processor for Biomedical Applications. CoRR Vijay Pratap Sharma, Annu Kumar, Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma
2026	J	`jnl`	C-SIMD: CORDIC-Driven SIMD Processing Element for Resource-Efficient Multi-Precision Deep Learning Inference. IEEE Access Vasundhara Trivedi, Gopal Raut, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar
2026	J	`jnl`	CIM-Enabled MBRO PUF: Integrating Multistage BRO and Reconfigurable SRAM for Edge Security Applications. IEEE Internet Things J. Neha Maheshwari, Brij B. Gupta, Santosh Kumar Vishvakarma
2026	J	`jnl`	CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications. CoRR Sonu Kumar, Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma
2026	J	`jnl`	Gated logic controlled 10T-SRAM for low-power bidirectional ring oscillators. Integr. Neha Maheshwari, Ambika Prasad Shah, Santosh Kumar Vishvakarma
2026	Misc	`conf`	PRISM: Photonic Reconfigurable In-Situ Memory for Next-Gen AI Workloads. VLSID Pratham Sharma, Santosh Kumar Vishvakarma
2026	Misc	`conf`	RAMAN: Resource-Efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-DesigN. VLSID Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma
2026	J	`jnl`	SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency. CoRR Sonu Kumar, Lavanya Vinnakota, Mukul Lokhande, Santosh Kumar Vishvakarma, Adam Teman
2026	Misc	`conf`	XR-NPE: High-Throughput Mixed-Precision SIMD Neural Processing Engine for Extended Reality Perception Workloads. VLSID Tejas Chaudhari, Akarsh J, Tanushree Dewangan, Mukul Lokhande, Santosh Kumar Vishvakarma
2025	—	`conf`	Area-Optimized 2D Interleaved Adder Tree Design for Sparse DCIM Edge Processing. ISQED Akash Sankhe, Mukul Lokhande, Radheshyam Sharma, Santosh Kumar Vishvakarma
2025	J	`jnl`	Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation. CoRR Mukul Lokhande, Tanushree Dewangan, Mohd Sharik Mansoori, Tejas Chaudhari, Akarsh J., Damayanti Lokhande, Adam Teman, Santosh Kumar Vishvakarma
2025	J	`jnl`	CORDIC Is All You Need. CoRR Omkar Kokane, Adam Teman, Anushka Jha, Guru Prasath SL, Gopal Raut, Mukul Lokhande, S. V. Jaya Chand, Tanushree Dewangan, Santosh Kumar Vishvakarma
2025	J	`jnl`	Configurable Multiport Memory Architecture for High-Speed Data Communication. IEEE Embed. Syst. Lett. Narendra Singh Dhakad, Santosh Kumar Vishvakarma
2025	J	`jnl`	FERMI-ML: A Flexible and Resource-Efficient Memory-In-Situ SRAM Macro for TinyML acceleration. CoRR Mukul Lokhande, Akash Sankhe, S. V. Jaya Chand, Santosh Kumar Vishvakarma
2025	J	`jnl`	Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads. IEEE Trans. Very Large Scale Integr. Syst. Mukul Lokhande, Gopal Raut, Santosh Kumar Vishvakarma
2025	C	`conf`	LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine. ISCAS Omkar Kokane, Mukul Lokhande, Gopal Raut, Adam Teman, Santosh Kumar Vishvakarma
2025	J	`jnl`	POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration. CoRR Mukul Lokhande, Santosh Kumar Vishvakarma
2025	J	`jnl`	QForce-RL: Quantized FPGA-Optimized Reinforcement Learning Compute Engine. CoRR Anushka Jha, Tanushree Dewangan, Mukul Lokhande, Santosh Kumar Vishvakarma
2025	J	`jnl`	RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN. CoRR Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma
2025	J	`jnl`	ReLACE: A Resource-Efficient Low-Latency Cortical Acceleration Engine. CoRR Sonu Kumar, Arjun S. Nair, Bhawna Chaudhary, Mukul Lokhande, Santosh Kumar Vishvakarma
2025	J	`jnl`	Res-DPU: Resource-shared Digital Processing-in-memory Unit for Edge-AI Workloads. CoRR Mukul Lokhande, Narendra Singh Dhakad, Seema Chouhan, Akash Sankhe, Santosh Kumar Vishvakarma
2025	—	`conf`	Retrospective: A CORDIC Based Configurable Activation Function for NN Applications. ISVLSI Omkar Kokane, Gopal Raut, Salim Ullah, Mukul Lokhande, Adam Teman, Akash Kumar, Santosh Kumar Vishvakarma
2025	J	`jnl`	Retrospective: A CORDIC Based Configurable Activation Function for NN Applications. CoRR Omkar Kokane, Gopal Raut, Salim Ullah, Mukul Lokhande, Adam Teman, Akash Kumar, Santosh Kumar Vishvakarma
2025	J	`jnl`	XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads. CoRR Tejas Chaudhari, Akarsh J., Tanushree Dewangan, Mukul Lokhande, Santosh Kumar Vishvakarma
2024	J	`jnl`	A Precision-Aware Neuron Engine for DNN Accelerators. SN Comput. Sci. Sudheer Vishwakarma, Gopal Raut, Sonu Jaiswal, Santosh Kumar Vishvakarma, Dhruva Ghai
2024	J	`jnl`	Configurable Multi-Port Memory Architecture for High-Speed Data Communication. CoRR Narendra Singh Dhakad, Santosh Kumar Vishvakarma
2024	J	`jnl`	Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads. CoRR Mukul Lokhande, Gopal Raut, Santosh Kumar Vishvakarma
2024	—	`conf`	HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine. VDAT Omkar Kokane, Prabhat Sati, Mukul Lokhande, Santosh Kumar Vishvakarma
2024	J	`jnl`	HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine. CoRR Omkar Kokane, Prabhat Sati, Mukul Lokhande, Santosh Kumar Vishvakarma
2024	J	`jnl`	HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator. CoRR Sonu Kumar, Komal Gupta, Gopal Raut, Mukul Lokhande, Santosh Kumar Vishvakarma
2024	J	`jnl`	In-Memory Computing with 6T SRAM for Multi-operator Logic Design. Circuits Syst. Signal Process. Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma
2024	J	`jnl`	QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit. IEEE Access Neha Ashar, Gopal Raut, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar
2024	J	`jnl`	SHA-CNN: Scalable Hierarchical Aware Convolutional Neural Network for Edge AI. CoRR Narendra Singh Dhakad, Yuvnish Malhotra, Santosh Kumar Vishvakarma, Kaushik Roy
2023	J	`jnl`	A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic. J. Circuits Syst. Comput. Ravi Kumar, Pooja Bohara, Krishna Thakur, Santosh Kumar Vishvakarma
2023	—	`conf`	A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators. IFIPIoT (1) Sudheer Vishwakarma, Gopal Raut, Narendra Singh Dhakad, Santosh Kumar Vishvakarma, Dhruva Ghai
2023	J	`jnl`	A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency. J. Circuits Syst. Comput. Ravi Kumar, Rajasekhar Nagulapalli, Santosh Kumar Vishvakarma
2023	J	`jnl`	An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Gopal Raut, Saurabh Karkun, Santosh Kumar Vishvakarma
2023	J	`jnl`	An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning. IEEE Access Sumiran Mehra, Gopal Raut, Ribhu Das Purkayastha, Santosh Kumar Vishvakarma, Anton Biasizzo
2023	J	`jnl`	Clock Gating-Based Effectual Realization of Stochastic Hyperbolic Tangent Function for Deep Neural Hardware Accelerators. Circuits Syst. Signal Process. Gunjan Rajput, V. Logashree, Kunika Naresh Biyani, Santosh Kumar Vishvakarma
2023	Misc	`conf`	Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application. VLSID Mohd Sakib Ansari S, Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
2023	J	`jnl`	Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators. Circuits Syst. Signal Process. Gopal Raut, Jogesh Mukala, Vishal Sharma, Santosh Kumar Vishvakarma
2023	J	`jnl`	Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array. IEEE J. Emerg. Sel. Topics Circuits Syst. Kavitha Soundrapandiyan, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal
2023	J	`jnl`	Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs. Circuits Syst. Signal Process. Vasundhara Trivedi, Khushbu Lalwani, Gopal Raut, Avikshit Khomane, Neha Ashar, Santosh Kumar Vishvakarma
2022	—	`conf`	An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. VDAT S. Kavitha, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal
2022	J	`jnl`	An accurate and noninvasive skin cancer screening based on imaging technique. Int. J. Imaging Syst. Technol. Gunjan Rajput, Shashank Agrawal, Gopal Raut, Santosh Kumar Vishvakarma
2022	J	`jnl`	BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator. Circuits Syst. Signal Process. Harsh Chhajed, Gopal Raut, Narendra Singh Dhakad, Sudheer Vishwakarma, Santosh Kumar Vishvakarma
2022	J	`jnl`	Data multiplexed and hardware reused architecture for deep neural network accelerator. Neurocomputing Gopal Raut, Anton Biasizzo, Narendra Singh Dhakad, Neha Gupta, Gregor Papa, Santosh Kumar Vishvakarma
2022	J	`jnl`	Early breast cancer diagnosis using cogent activation function-based deep learning implementation on screened mammograms. Int. J. Imaging Syst. Technol. Gunjan Rajput, Shashank Agrawal, Kunika Naresh Biyani, Santosh Kumar Vishvakarma
2022	—	`conf`	Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array. ACM Great Lakes Symposium on VLSI Varun Bhatnagar, Gopal Raut, Santosh Kumar Vishvakarma
2022	J	`jnl`	SCAN: Streamlined Composite Activation Function Unit for Deep Neural Accelerators. Circuits Syst. Signal Process. Gunjan Rajput, Kunika Naresh Biyani, V. Logashree, Santosh Kumar Vishvakarma
2022	—	`conf`	SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. ISVLSI Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu
2021	J	`jnl`	A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies. IEEE Access Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar
2021	J	`jnl`	Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture". IEEE Open J. Circuits Syst. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar
2021	Misc	`conf`	Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. COMSNETS Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, J. Soumya, M. B. Srinivas, Phaneendra K. Yalavarthy, Abhinav Kumar, V. Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi
2021	J	`jnl`	RECON: Resource-Efficient CORDIC-Based Neuron Architecture. IEEE Open J. Circuits Syst. Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar
2021	J	`jnl`	VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators. Microprocess. Microsystems Gunjan Rajput, Gopal Raut, Mahesh Chandra, Santosh Kumar Vishvakarma
2021	—	`conf`	Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. ACM Great Lakes Symposium on VLSI Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard
2020	J	`jnl`	A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture. Circuits Syst. Signal Process. Gopal Raut, Ambika Prasad Shah, Vishal Sharma, Gunjan Rajput, Santosh Kumar Vishvakarma
2020	—	`conf`	A CORDIC Based Configurable Activation Function for ANN Applications. ISVLSI Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar
2020	J	`jnl`	A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application. J. Circuits Syst. Comput. Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar, Gaurav Singh, Santosh Kumar Vishvakarma
2020	J	`jnl`	An improved current mode logic latch for high-speed applications. Int. J. Commun. Syst. Mahesh Kumawat, Abhishek Kumar Upadhyay, Sanjay Sharma, Ravi Kumar, Gaurav Singh, Santosh Kumar Vishvakarma
2020	J	`jnl`	Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications. J. Electron. Test. Ambika Prasad Shah, Santosh Kumar Vishvakarma, Michael Hübner
2019	—	`conf`	A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell. VDAT Neha Gupta, Jitesh Prasad, Rana Sagar Kumar, Gunjan Rajput, Santosh Kumar Vishvakarma
2019	J	`jnl`	An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi
2019	—	`conf`	An Ultra Low Power AES Architecture for IoT. VDAT Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma
2019	J	`jnl`	An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network. Microelectron. J. Prachi Sanvale, Neha Gupta, Vaibhav Neema, Ambika Prasad Shah, Santosh Kumar Vishvakarma
2019	J	`jnl`	An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications. Microelectron. J. Sajid Khan, Ambika Prasad Shah, Neha Gupta, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma
2019	—	`conf`	Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications. VDAT Ankur Beohar, Gopal Raut, Gunjan Rajput, Abhinav Vishwakarma, Ambika Prasad Shah, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
2019	—	`conf`	Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. VDAT Sajid Khan, Neha Gupta, Abhinav Vishwakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma
2019	—	`conf`	Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network. VDAT Gopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, Ankur Beohar, Santosh Kumar Vishvakarma
2019	—	`ch.`	IoT-Based Ambient Intelligence Microcontroller for Remote Temperature Monitoring. Guide to Ambient Intelligence in the IoT Environment Balwinder Raj, Jeetendra Singh, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan
2019	—	`conf`	Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell. VDAT Neha Gupta, Tanisha Gupta, Sajid Khan, Abhinav Vishwakarma, Santosh Kumar Vishvakarma
2019	J	`jnl`	SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit. IET Comput. Digit. Tech. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma
2019	—	`ed.`	VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers VDAT Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma
2018	—	`conf`	A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. VDAT Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, Santosh Kumar Vishvakarma, Abhijit Karmakar, Raj Singh
2018	—	`conf`	A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. VDAT Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma
2018	J	`jnl`	A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes. Int. J. Circuit Theory Appl. Vishal Sharma, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan, Kari Halonen
2018	J	`jnl`	An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells. Microelectron. Reliab. Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma
2018	J	`jnl`	Robust task-space motion control of a mobile manipulator using a nonlinear control with an uncertainty estimator. Comput. Electr. Eng. S. Mishra, Pandurang S. Londhe, Mohan Santhakumar, Santosh Kumar Vishvakarma, B. M. Patre
2018	C	`conf`	Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. ISCAS Aditya Japa, T. Nagateja, Santosh Kumar Vishvakarma, Yellappa Palagani, Jun Rim Choi, Ramesh Vaddi
2018	J	`jnl`	Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integr. Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma
2018	J	`jnl`	Ultra-Low Power High Stability 8T SRAM for Application in Object Tracking System. IEEE Access Pooran Singh, Santosh Kumar Vishvakarma
2017	Misc	`conf`	A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. VLSID Bhupendra Singh Reniwal, Pooran Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma
2017	J	`jnl`	Design and investigation of variability aware sense amplifier for low power, high speed SRAM. Microelectron. J. Bhupendra Singh Reniwal, Praneet Bhatia, Santosh Kumar Vishvakarma
2017	J	`jnl`	Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications. J. Low Power Electron. Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma
2017	—	`conf`	LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits. VDAT Ambika Prasad Shah, Nandakishor Yadav, Santosh Kumar Vishvakarma
2016	J	`jnl`	A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations. Microelectron. J. C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
2016	J	`jnl`	A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. IEEE Trans. Very Large Scale Integr. Syst. C. B. Kushwah, Santosh Kumar Vishvakarma
2016	—	`conf`	Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET. iNIS Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma
2016	—	`conf`	Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter. iNIS Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav, Santosh Kumar Vishvakarma
2016	J	`jnl`	Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications. Circuits Syst. Signal Process. C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
2016	J	`jnl`	Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi
2015	—	`conf`	An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. VDAT Praneet Bhatia, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
2015	J	`jnl`	Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron. J. Dheeraj Sharma, Santosh Kumar Vishvakarma
2015	—	`conf`	Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I ACM Great Lakes Symposium on VLSI Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi
2015	—	`conf`	Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs. iNIS Neha Jagwani, Vikas Vijayvargiya, Santosh Kumar Vishvakarma
2015	—	`conf`	Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity. iNIS Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal, V. Sharma, C. B. Khuswah, Devesh Dwivedi
2014	—	`conf`	A sub-threshold eight transistor (8T) SRAM cell design for stability improvement. ICICDT C. B. Kushwah, Santosh Kumar Vishvakarma
2014	—	`conf`	Single-ended sub-threshold finfet 7T SRAM cell without boosted supply. ICICDT C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi
2013	—	`conf`	Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM. VDAT Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma
2012	J	`jnl`	Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions. Microelectron. J. Dheeraj Sharma, Santosh Kumar Vishvakarma
2012	—	`conf`	Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin. VDAT Chandrabhan Kushwah, Santosh Kumar Vishvakarma
2011	J	`jnl`	Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlN Microelectron. J. Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta