Santanu Chattopadhyay

165 papers A* 2A 3B 1C 15Misc 25Journal 66Unranked 52

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Thermal and Congestion-aware Deadlock-free Application-specific Novel Halted Routing Strategy in 3D NoCs. Integr. Priyajit Mukherjee, Sayani Ghosh, Hafizur Rahaman, Santanu Chattopadhyay
2025	J	`jnl`	Performance evaluation for accelerated and efficient prediction of different regression models aggravated with BPSO for enhancing area efficiency through state encoding in sequential circuits. Swarm Evol. Comput. Kaushik Khatua, Santanu Chattopadhyay, Anindya Sundar Dhar
2024	J	`jnl`	Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ramesh Sambangi, Kanchan Manna, Vinay Chakravarthi Gogineni, Santanu Chattopadhyay, Sudipta Mahapatra
2023	J	`jnl`	Application Mapping Onto Manycore Processor Architectures Using Active Search Framework. IEEE Trans. Very Large Scale Integr. Syst. Ramesh Sambangi, Arun Sammit Pandey, Kanchan Manna, Sudipta Mahapatra, Santanu Chattopadhyay
2022	J	`jnl`	A Cellular Automata Guided Finite-State-Machine Watermarking Strategy for IP Protection of Sequential Circuits. IEEE Trans. Emerg. Top. Comput. Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
2022	J	`jnl`	Conformance Testing for Finite State Machines Guided by Deep Neural Network. J. Circuits Syst. Comput. Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta
2022	Misc	`conf`	Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking. VLSID Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta, Debesh K. Das, Bhargab B. Bhattacharya
2021	—	`conf`	A Deep Neural Network Guided Testing Approach for Finite State Machines. ISDCS Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta
2021	J	`jnl`	Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption. IEEE Trans. Emerg. Top. Comput. Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay
2021	J	`jnl`	Embedding delay-based physical unclonable functions in networks-on-chip. IET Circuits Devices Syst. Prasad Nagabhushanamgari, Vikash Sehwag, Indrajit Chakrabarti, Santanu Chattopadhyay
2021	J	`jnl`	LPNet: A DNN based latency prediction technique for application mapping in Network-on-Chip design. Microprocess. Microsystems Ramesh Sambangi, Hitesh Manghnani, Santanu Chattopadhyay
2020	—	`conf`	A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing. ISDCS Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya
2020	A	`conf`	A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access. DATE Rajit Karmakar, Santanu Chattopadhyay
2020	J	`jnl`	A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits. IEEE Trans. Circuits Syst. II Express Briefs Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
2020	J	`jnl`	A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection. Integr. Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
2020	A	`conf`	Hardware IP Protection Using Logic Encryption and Watermarking. ITC Rajit Karmakar, Santanu Chattopadhyay
2020	—	`conf`	On Securing Scan Obfuscation Strategies Against ScanSAT Attack. ISQED Rajit Karmakar, Santanu Chattopadhyay
2020	J	`jnl`	Task mapping and flow priority assignment of real-time industrial applications for network-on-chip based design. Microprocess. Microsystems Ajay Khare, Chinmay Patil, Santanu Chattopadhyay
2020	J	`jnl`	Thermal-aware detour routing in 3D NoCs. J. Parallel Distributed Comput. Priyajit Mukherjee, Navonil Chatterjee, Santanu Chattopadhyay
2019	A*	`conf`	A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis. DAC Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
2019	C	`conf`	A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis. TENCON Kaushik Khatua, Hillol Maity, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya
2019	C	`conf`	Enhanced Schedulability via Minimal Routing with Mapping and Priority Assignment for Real-Time Network-on-chip. TENCON Ajay Khare, Irene Anna Boben, Santanu Chattopadhyay
2019	—	`conf`	Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach. ICIT Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya
2019	C	`conf`	Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure. ISCAS Rajit Karmakar, Santanu Chattopadhyay, Mrityunjoy Chakraborty
2019	J	`jnl`	Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip. CoRR N. Prasad, Navonil Chatterjee, Santanu Chattopadhyay, Indrajit Chakrabarti
2019	J	`jnl`	Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems. ACM J. Emerg. Technol. Comput. Syst. Kanchan Manna, Chatla Swami Sagar, Santanu Chattopadhyay, Indranil Sengupta
2019	J	`jnl`	Thermal-aware task allocation and scheduling for periodic real-time applications in mesh-based heterogeneous NoCs. Real Time Syst. Priyajit Mukherjee, Kokil Jain, Santanu Chattopadhyay
2018	J	`jnl`	An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. N. Prasad, Indrajit Chakrabarti, Santanu Chattopadhyay
2018	J	`jnl`	Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution. Integr. Priyajit Mukherjee, Sandeep D'Souza, Santanu Chattopadhyay
2018	J	`jnl`	Design and evaluation of ZMesh topology for on-chip interconnection networks. J. Parallel Distributed Comput. N. Prasad, Priyajit Mukherjee, Santanu Chattopadhyay, Indrajit Chakrabarti
2018	J	`jnl`	Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits. CoRR Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
2018	—	`conf`	Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC. VDAT Ajay Khare, Chinmay Patil, Manikanta Nallamalli, Santanu Chattopadhyay
2018	C	`conf`	On Finding Suitable Key-Gate Locations In Logic Encryption. ISCAS Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay
2018	J	`jnl`	Reliability-aware application mapping onto mesh based Network-on-Chip. Integr. Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay
2018	J	`jnl`	Task mapping and scheduling for network-on-chip based multi-core platform with transient faults. J. Syst. Archit. Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay
2018	—	`conf`	Thermal Aware Application Mapping and Frequency Scaling for Mesh-Based Network-On-Chip Design. iSES Raghav Sonavane, Gobburi Sai Kashyap, Santanu Chattopadhyay
2018	J	`jnl`	Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design. IEEE Trans. Computers Kanchan Manna, Priyajit Mukherjee, Santanu Chattopadhyay, Indranil Sengupta
2017	Misc	`conf`	A New Logic Encryption Strategy Ensuring Key Interdependency. VLSID Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta
2017	J	`jnl`	Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform. J. Syst. Archit. Navonil Chatterjee, Suraj Paul, Priyajit Mukherjee, Santanu Chattopadhyay
2017	—	`conf`	Enhancing security of logic encryption using embedded key generation unit. ITC-Asia Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
2017	J	`jnl`	Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform. ACM Trans. Embed. Comput. Syst. Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay
2017	J	`jnl`	Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design. Integr. Priyajit Mukherjee, Santanu Chattopadhyay
2017	J	`jnl`	Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture. J. Circuits Syst. Comput. J. Soumya, K. Niranjan Babu, Santanu Chattopadhyay
2017	C	`conf`	Runtime mitigation of illegal packet request attacks in Networks-on-Chip. ISCAS N. Prasad, Rajit Karmakar, Santanu Chattopadhyay, Indrajit Chakrabarti
2017	J	`jnl`	Temperature and data size trade-off in dictionary based test data compression. Integr. Rajit Karmakar, Santanu Chattopadhyay
2016	—	`conf`	A reliability aware application mapping onto mesh based Network-on-Chip. RAIT Navonil Chatterjee, Sheshivardhan Reddy, Shilpa Reddy, Santanu Chattopadhyay
2016	—	`conf`	A strategy for fault tolerant reconfigurable Network-on-Chip design. VDAT Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay
2016	—	`conf`	An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design. RAIT Priyajit Mukherjee, Santanu Chattopadhyay
2016	J	`jnl`	In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers. IEEE Trans. Very Large Scale Integr. Syst. Bibhas Ghoshal, Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta
2016	J	`jnl`	Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels. ACM Trans. Archit. Code Optim. Sandeep D'Souza, Soumya J., Santanu Chattopadhyay
2016	J	`jnl`	Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design. ACM Trans. Embed. Comput. Syst. Kanchan Manna, Shivam Swami, Santanu Chattopadhyay, Indranil Sengupta
2016	Misc	`conf`	Optimization of the IEEE 1687 access network for hybrid access schedules. VTS Srinivasa Shashank Nuthakki, Rajit Karmakar, Santanu Chattopadhyay, Krishnendu Chakrabarty
2016	J	`jnl`	Small Test Set Generation with High Diagnosability. J. Circuits Syst. Comput. Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2016	—	`conf`	Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip. ISVLSI Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta
2016	—	`conf`	Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs. ISVLSI Kanchan Manna, Chatla Swamy Sagar, Santanu Chattopadhyay, Indranil Sengupta
2016	Misc	`conf`	Thermal-Safe Schedule Generation for System-on-Chip Testing. VLSID Rajit Karmakar, Santanu Chattopadhyay
2015	J	`jnl`	A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip. J. Circuits Syst. Comput. Pradip Kumar Sahu, Kanchan Manna, Tapan Shah, Santanu Chattopadhyay
2015	—	`conf`	A constructive heuristic for application mapping onto an express channel based Network-on-Chip. VDAT Sandeep D'Souza, J. Soumya, Santanu Chattopadhyay
2015	C	`conf`	A hardware based low temperature solution for VLSI testing using decompressor side masking. ISCAS Arpita Dutta, Subhadip Kundu, Santanu Chattopadhyay, Bijit Kumar Das
2015	—	`conf`	An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets. ATS Srinivasa Shashank Nuthakki, Santanu Chattopadhyay
2015	J	`jnl`	Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores. J. Syst. Archit. J. Soumya, Srijan Tiwary, Santanu Chattopadhyay
2015	C	`conf`	Fault tolerant mesh based Network-on-Chip architecture. ISCAS Navonil Chatterjee, Santanu Chattopadhyay
2015	—	`conf`	GA based diagnostic test pattern generation for transition faults. VDAT Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2015	J	`jnl`	Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes. J. Syst. Archit. J. Soumya, Kundan Kumar, Santanu Chattopadhyay
2015	—	`conf`	Particle swarm optimization approach for low temperature BIST. VDAT Arpita Dutta, Santanu Chattopadhyay
2015	—	`conf`	Power- and thermal-aware testing of VLSI circuits and systems. VDAT Santanu Chattopadhyay
2015	J	`jnl`	Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip. Microprocess. Microsystems N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti
2015	J	`jnl`	Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment. IEEE Trans. Very Large Scale Integr. Syst. Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2015	—	`conf`	TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning. ISVLSI Kanchan Manna, Vadapalli Shanmukha Sri Teja, Santanu Chattopadhyay, Indranil Sengupta
2015	—	`conf`	Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints. ATS Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
2015	C	`conf`	Test set customization for improved fault diagnosis without sacrificing coverage. ISCAS Srinivasa Shashank Nuthakki, Santanu Chattopadhyay, Mrityunjoy Chakraborty
2015	Misc	`conf`	Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach. VTS Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
2015	Misc	`conf`	Thermal-Aware Test Data Compression Using Dictionary Based Coding. VLSID Rajit Karmakar, Santanu Chattopadhyay
2015	J	`jnl`	Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation. Int. J. High Perform. Syst. Archit. Kanchan Manna, Chakradhar Reddy Veeramreddy, Santanu Chattopadhyay, Indranil Sengupta
2015	J	`jnl`	Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling. Integr. Rajit Karmakar, Santanu Chattopadhyay
2015	—	`conf`	ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms. iNIS N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti
2014	—	`conf`	A locally reconfigurable Network-on-Chip architecture and application mapping onto it. VDAT Soumya J., Ashish Sharma, Santanu Chattopadhyay
2014	—	`conf`	A spare link based reliable Network-on-Chip design. VDAT Navonil Chatterjee, N. Prasad, Santanu Chattopadhyay
2014	C	`conf`	A spare router based reliable Network-on-Chip design. ISCAS Navonil Chatterjee, Santanu Chattopadhyay, Kanchan Manna
2014	J	`jnl`	Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. Pradip Kumar Sahu, Tapan Shah, Kanchan Manna, Santanu Chattopadhyay
2014	J	`jnl`	Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip. J. Syst. Archit. Pradip Kumar Sahu, Kanchan Manna, Nisarg Shah, Santanu Chattopadhyay
2014	J	`jnl`	Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. Subhadip Kundu, Aniket Jha, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2014	J	`jnl`	Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. Soumya J., Ashish Sharma, Santanu Chattopadhyay
2014	—	`conf`	Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model. VDAT Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
2014	C	`conf`	Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip. VLSI-SoC Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta
2014	Misc	`conf`	Tutorial T7A: Techniques for Network-on-Chip (NoC) Design and Test. VLSID Santanu Chattopadhyay
2013	J	`jnl`	A Metric for Test Set Characterization and Customization Toward Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhadip Kundu, Sankhadeep Pal, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2013	J	`jnl`	A survey on application mapping strategies for Network-on-Chip design. J. Syst. Archit. Pradip Kumar Sahu, Santanu Chattopadhyay
2013	B	`conf`	Aggresive scan chain masking for improved diagnosis of multiple scan chain failures. ETS Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2013	A*	`conf`	An ATE assisted DFD technique for volume diagnosis of scan chains. DAC Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2013	J	`jnl`	Application-Specific Network-on-Chip synthesis with flexible router Placement. J. Syst. Archit. J. Soumya, Santanu Chattopadhyay
2013	—	`conf`	Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization. VDAT Kanchan Manna, Shailesh Singh, Santanu Chattopadhyay, Indranil Sengupta
2013	—	`conf`	Thermal Aware Don't Care Filling to Reduce Peak Temperature and Thermal Variance during Testing. Asian Test Symposium Arpita Dutta, Subhadip Kundu, Santanu Chattopadhyay
2012	Misc	`conf`	A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection. VLSI Design Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2012	—	`conf`	An Efficient Technique for Longest Prefix Matching in Network Routers. VDAT Rekha Govindaraj, Indranil Sengupta, Santanu Chattopadhyay
2012	—	`conf`	Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization. ISED Pradip Kumar Sahu, Ashish Sharma, Santanu Chattopadhyay
2012	—	`conf`	Confidence Based Power Aware Testing. ISED Tapas Kumar Maiti, Subhadip Kundu, Arpita Dutta, Santanu Chattopadhyay
2012	J	`jnl`	Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing. Integr. S. Krishna Kumar, Subhadip Kundu, Santanu Chattopadhyay
2012	J	`jnl`	Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router. Microprocess. Microsystems Santanu Kundu, J. Soumya, Santanu Chattopadhyay
2012	J	`jnl`	Efficient don't care filling and scan chain masking for low-power testing. Int. J. Comput. Aided Eng. Technol. Subhadip Kundu, Santanu Chattopadhyay
2012	J	`jnl`	Multiplexer-Based Multi-Level Circuit Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. Sambhu Nath Pradhan, Santanu Chattopadhyay
2012	—	`conf`	Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip. VDAT Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta, Santanu Chattopadhyay
2012	—	`ed.`	Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings VDAT Hafizur Rahaman, Sanatan Chattopadhyay, Santanu Chattopadhyay
2012	J	`jnl`	Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique. IET Comput. Digit. Tech. A. Mitra, Santanu Chattopadhyay
2011	J	`jnl`	And-or-XOR Network Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
2011	—	`conf`	Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization. ISVLSI Pradip Kumar Sahu, Putta Venkatesh, Sunilraju Gollapalli, Santanu Chattopadhyay
2011	—	`conf`	Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits. ISVLSI Santanu Kundu, Santanu Chattopadhyay
2011	—	`conf`	Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis. ISVLSI J. Soumya, Putta Venkatesh, Santanu Chattopadhyay
2011	J	`jnl`	Low power finite state machine synthesis using power-gating. Integr. Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
2011	Misc	`conf`	Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. VLSI Design Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
2010	A	`conf`	Customizing pattern set for test power reduction via improved X-identification and reordering. ISLPED S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay
2010	—	`conf`	Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing. Asian Test Symposium S. Krishna Kumar, S. Kaundinya, Santanu Chattopadhyay
2009	—	`conf`	A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic. ARTCom Santanu Kundu, Kanchan Manna, Shobhit Gupta, Kundan Kumar, Ritesh Parikh, Santanu Chattopadhyay
2009	—	`conf`	Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing. ARTCom S. Krishna Kumar, P. Uday Bhaskar, Santanu Chattopadhyay, Pradip Mandal
2009	—	`conf`	Efficient Don't Care Filling for Power Reduction during Testing. ARTCom Subhadip Kundu, Santanu Chattopadhyay
2009	J	`jnl`	Genetic algorithm-based FSM synthesis with area-power trade-offs. Integr. Saurabh Chaudhury, Krishna Teja Sistla, Santanu Chattopadhyay
2009	J	`jnl`	State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis. J. Low Power Electron. Saurabh Chaudhury, J. Srinivasa Rao, Santanu Chattopadhyay
2009	Misc	`conf`	Synthesis & Testing for Low Power. VLSI Design Ajit Pal, Santanu Chattopadhyay
2009	—	`conf`	Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption. Asian Test Symposium Subhadip Kundu, S. Krishna Kumar, Santanu Chattopadhyay
2008	—	`conf`	A Novel Technique to Reduce both Leakage and Peak Power during Scan Testing. ICIIS Subhadip Kundu, Santanu Chattopadhyay, Kanchan Manna
2008	—	`conf`	AND-XOR Network Synthesis with Area-Power Trade-off. ICIIS Sambhu Nath Pradhan, Santanu Chattopadhyay
2008	C	`conf`	An efficient finite precision realization of the block adaptive decision feedback equalizer. ISCAS Rafiahamed Shaik, Mrityunjoy Chakraborty, Santanu Chattopadhyay
2008	C	`conf`	An efficient greedy approach to PLA folding. ISCAS Mayur Bubna, Naresh Shenoy, Santanu Chattopadhyay
2008	C	`conf`	Don't care filling for power minimization in VLSI circuit testing. ISCAS Tapas K. Maiti, Santanu Chattopadhyay
2008	—	`conf`	Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. ISVLSI Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
2008	—	`conf`	Mesh-of-Tree Based Scalable Network-on-Chip Architecture. ICIIS Santanu Kundu, Radha Purnima Dasari, Santanu Chattopadhyay, Kanchan Manna
2008	—	`conf`	Mesh-of-tree deterministic routing for network-on-chip architecture. ACM Great Lakes Symposium on VLSI Santanu Kundu, Santanu Chattopadhyay
2008	J	`jnl`	Network-on-chip architecture design based on mesh-of-tree deterministic routing topology. Int. J. High Perform. Syst. Archit. Santanu Kundu, Santanu Chattopadhyay
2008	—	`conf`	Three-level AND-OR-XOR network synthesis: A GA based approach. APCCAS Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
2007	C	`conf`	A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. VLSI-SoC Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay
2007	—	`conf`	Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling. ICCTA Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay
2007	C	`conf`	Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs. ISCAS Chandan Giri, Santanu Chattopadhyay
2007	—	`conf`	Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering. ATS Chandan Giri, Pradeep Kumar Choudhary, Santanu Chattopadhyay
2007	—	`conf`	Test Data Compression by Spilt-VIHC (SVIHC). ICCTA Chandan Giri, B. Mallikarjuna Rao, Santanu Chattopadhyay
2007	—	`conf`	Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach. ICIC (2) Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay
2006	—	`conf`	Synthesis of Finite State Machines for Low Power and Testability. APCCAS Saurabh Chaudhury, Santanu Chattopadhyay, J. Srinivasa Rao
2005	Misc	`conf`	A Combinational Logic Mapper for Actel's SX/AX Family. VLSI Design Santanu Chattopadhyay, Manas Kumar Dewangan
2005	J	`jnl`	Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis?A Genetic Algorithm Approach. Comput. J. Santanu Chattopadhyay
2005	—	`conf`	Flip-flop chaining architecture for power-efficient scan during test application. Asian Test Symposium Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay
2004	Misc	`conf`	Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs. VLSI Design D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar
2004	—	`conf`	Model checking on state transition diagram. ASP-DAC Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay
2003	Misc	`conf`	Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. VLSI Design Santanu Chattopadhyay, Naveen Choudhary
2003	Misc	`conf`	Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips. VLSI Design Santanu Chattopadhyay, K. Sudarsana Reddy
2003	Misc	`conf`	Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach". VLSI Design Rohit Pandey, Santanu Chattopadhyay
2002	—	`conf`	Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata. Asian Test Symposium Santanu Chattopadhyay
2001	Misc	`conf`	A Novel Strategy to Test Core Based Designs. VLSI Design Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay
2001	J	`jnl`	Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator. IEEE Trans. Computers Prabir Dasgupta, Santanu Chattopadhyay, Parimal Pal Chaudhuri, Indranil Sengupta
2001	J	`jnl`	Theory and application of non-group cellular automata for message authentication. J. Syst. Archit. Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta
2000	Misc	`conf`	An ASIC for Cellular Automata Based Message Authentication. VLSI Design Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta
2000	Misc	`conf`	Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits. VLSI Design Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta
2000	J	`jnl`	Highly regular, modular, and cascadable design of cellular automata-based pattern classifier. IEEE Trans. Very Large Scale Integr. Syst. Santanu Chattopadhyay, Shelly Adhikari, Sabyasachi Sengupta, Mahua Pal
1998	J	`jnl`	Cellular-Automata-Array-Based Diagnosis of Board Level Faults. IEEE Trans. Computers Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
1998	Misc	`conf`	Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence. VLSI Design Santanu Chattopadhyay, Parimal Pal Chaudhuri
1998	Misc	`conf`	Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis. VLSI Design Santanu Chattopadhyay, Parimal Pal Chaudhuri
1998	—	`conf`	Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. Asian Test Symposium Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri
1997	J	`jnl`	KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
1997	Misc	`conf`	Parallel Decoder for Cellular Automata Based Byte Error Correcting Code. VLSI Design Santanu Chattopadhyay, Parimal Pal Chaudhuri
1996	J	`jnl`	CAA Decoder for Cellular Automata Based Byte Error Correcting Code. IEEE Trans. Computers Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri
1996	Misc	`conf`	Cellular automata based architecture of a database query processor. VLSI Design Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri
1996	Misc	`conf`	Programmable cellular automata based testbed for fault diagnosis in VLSI circuits. VLSI Design Sukumar Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri
1996	J	`jnl`	Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach. IEEE Trans. Computers Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
1995	Misc	`conf`	Board level fault diagnosis using cellular automata array. VLSI Design Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri
1995	Misc	`conf`	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture. VLSI Design Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
1994	J	`jnl`	A new look into the acquisition properties of a second-order digital phase locked loop. IEEE Trans. Commun. B. C. Sarkar, Santanu Chattopadhyay
1990	J	`jnl`	Symmetric lock-range multilevel quantized digital phase locked FM demodulator. IEEE Trans. Commun. B. C. Sarkar, Santanu Chattopadhyay