Sanroku Tsukamoto

24 papers Misc 1Journal 13Unranked 10
YearRankTypeTitle / Venue / Authors
2017 J jnl
Advances in Analog-to-Digital Converters over the Last Decade.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Sanroku Tsukamoto
2017 Misc conf
Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine.
CISIS
Satoshi Matsubara, Hirotaka Tamura, Motomu Takatsu, Danny Yoo, Behraz Vatankhahghadim, Hironobu Yamasaki, Toshiyuki Miyazawa, Sanroku Tsukamoto, Yasuhiro Watanabe, Kazuya Takemoto, Ali Sheikholeslami
2015 J jnl
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC.
IEEE J. Solid State Circuits
Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro
2014 — conf
7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique.
VLSIC
Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro
2014 J jnl
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS.
IEEE J. Solid State Circuits
Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto
2014 J jnl
A 7-bit 1-GS/s Flash ADC with Background Calibration.
IEICE Trans. Electron.
Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa
2013 — conf
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.
ISSCC
Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura
2013 J jnl
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.
IEEE J. Solid State Circuits
Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura
2012 — conf
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS.
VLSI-DAT
Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto
2012 J jnl
A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration.
IEICE Trans. Electron.
Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
2012 — conf
A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array.
VLSI-DAT
Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
2010 J jnl
A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration.
IEEE Trans. Biomed. Circuits Syst.
Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto
2010 — conf
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration.
ISSCC
Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto
2010 J jnl
A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda
2010 J jnl
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2010 J jnl
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.
IEICE Trans. Electron.
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2009 — conf
A 1 GHz CMOS comparator with dynamic offset control technique.
ASP-DAC
Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda
2009 — conf
A 6b 3GS/s flash ADC with background calibration.
CICC
Masashi Kijima, Kenji Ito, Kuniyoshi Kamei, Sanroku Tsukamoto
2009 — conf
Split capacitor DAC mismatch calibration in successive approximation ADC.
CICC
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2008 — conf
A dynamic offset control technique for comparator design in scaled CMOS technology.
CICC
Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda
2008 J jnl
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits
Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee
2007 — conf
A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing.
ISSCC
Masato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto
1998 J jnl
A CMOS 6-b, 400-MSample/s ADC with error correction.
IEEE J. Solid State Circuits
Sanroku Tsukamoto, William G. Schofield, Toshiaki Endo
1996 J jnl
A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI.
IEEE J. Solid State Circuits
Sanroku Tsukamoto, I. Dedic, Toshiaki Endo, K. y. Kikuta, K. Goto, O. Kobayashi