Sanjukta Bhanja

62 papers A* 2A 3C 3Misc 6Journal 29Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Enhancing biologically inspired hierarchical temporal memory with hardware-accelerated reflex memory. Neurocomputing Pavia Bera, Sabrina Hassan Moon, Jennifer Adorno, Dayane Alfenas Reis, Sanjukta Bhanja
2025	J	`jnl`	Enhancing Biologically Inspired Hierarchical Temporal Memory with Hardware-Accelerated Reflex Memory. CoRR Pavia Bera, Sabrina Hassan Moon, Jennifer Adorno, Dayane Alfenas Reis, Sanjukta Bhanja
2025	J	`jnl`	Quantification of Uncertainties in Probabilistic Deep Neural Network by Implementing Boosting of Variational Inference. CoRR Pavia Bera, Sanjukta Bhanja
2024	J	`jnl`	SPIMulator: A Spintronic Processing-in-memory Simulator for Racetracks. ACM Trans. Embed. Comput. Syst. Pavia Bera, Stephen Cahoon, Sanjukta Bhanja, Alex K. Jones
2023	J	`jnl`	Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT. IEEE Trans. Computers Sébastien Ollivier, Stephen Longofono, Prayash Dutta, Jingtong Hu, Sanjukta Bhanja, Alex K. Jones
2022	J	`jnl`	A Multi-domain Magneto Tunnel Junction for Racetrack Nanowire Strips. CoRR Prayash Dutta, Albert Lee, Kang L. Wang, Alex K. Jones, Sanjukta Bhanja
2022	A*	`conf`	CORUSCANT: Fast Efficient Processing-in-Racetrack Memories. MICRO Sébastien Ollivier, Stephen Longofono, Prayash Dutta, Jingtong Hu, Sanjukta Bhanja, Alex K. Jones
2022	J	`jnl`	Pinning Fault Mode Modeling for DWM Shifting. CoRR Kawsher A. Roxy, Stephen Longofono, Sébastien Ollivier, Sanjukta Bhanja, Alex K. Jones
2022	J	`jnl`	Pinning Fault Mode Modeling for DWM Shifting. IEEE Trans. Circuits Syst. II Express Briefs Kawsher A. Roxy, Stephen Longofono, Sébastien Ollivier, Sanjukta Bhanja, Alex K. Jones
2021	J	`jnl`	PIRM: Processing In Racetrack Memories. CoRR Sébastien Ollivier, Stephen Longofono, Prayash Dutta, Jingtong Hu, Sanjukta Bhanja, Alex K. Jones
2021	J	`jnl`	XDWM: A 2D Domain Wall Memory. CoRR Arifa Hoque, Alex K. Jones, Sanjukta Bhanja
2020	J	`jnl`	MatlabHTM: A sequence memory model of neocortical layers for anomaly detection. SoftwareX Ilia A. Bautista Adames, Sudeep Sarkar, Sanjukta Bhanja
2019	A	`conf`	Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories. DSN Sébastien Ollivier, Donald Kline Jr., Kawsher A. Roxy, Rami G. Melhem, Sanjukta Bhanja, Alex K. Jones
2019	—	`conf`	The Power of Orthogonality. ISVLSI Sébastien Ollivier, Donald Kline Jr., Kawsher A. Roxy, Rami G. Melhem, Sanjukta Bhanja, Alex K. Jones
2018	J	`jnl`	Non-Boolean Computing with Spintronic Devices. Found. Trends Electron. Des. Autom. Kawsher A. Roxy, Sanjukta Bhanja
2017	—	`conf`	Integrating emerging memory technologies into undergraduate logic design course: The impact of context based teaching. MSE Arifa Hoque, William Sutton, Kawsher A. Roxy, Sanjukta Bhanja
2017	—	`conf`	Variability tolerant reading of nanomagnetic energy minimizing co-processor. MWSCAS Kawsher A. Roxy, Sanjukta Bhanja
2016	J	`jnl`	MRAM PUF: Using Geometric and Resistive Variations in MRAM Cells. ACM J. Emerg. Technol. Comput. Syst. Jayita Das, Kevin Scott, Sanjukta Bhanja
2016	—	`conf`	Survey of Emerging Technology Based Physical Unclonable Funtions. ACM Great Lakes Symposium on VLSI Ilia A. Bautista Adames, Jayita Das, Sanjukta Bhanja
2015	J	`jnl`	Guest Editorial: Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies. ACM J. Emerg. Technol. Comput. Syst. Aida Todri-Sanial, Sanjukta Bhanja
2014	—	`book`	Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives Field-Coupled Nanocomputing Neal G. Anderson, Sanjukta Bhanja
2014	J	`jnl`	Nano Magnetic STT-Logic Partitioning for Optimum Performance. IEEE Trans. Very Large Scale Integr. Syst. Jayita Das, Syed M. Alam, Sanjukta Bhanja
2014	—	`ch.`	STT-Based Non-Volatile Logic-in-Memory Framework. Field-Coupled Nanocomputing Jayita Das, Syed M. Alam, Sanjukta Bhanja
2012	—	`conf`	Evaluation of circuit styles and VLSI logic designs of pentacene OTFTs. MWSCAS Sneta Mishra, Sanjukta Bhanja
2012	—	`conf`	Non-destructive variability tolerant differential read for non-volatile logic. MWSCAS Jayita Das, Syed M. Alam, Sanjukta Bhanja
2012	J	`jnl`	Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Jayita Das, Syed M. Alam, Sanjukta Bhanja
2011	C	`conf`	A review of magnetic cellular automata systems. ISCAS Sanjukta Bhanja, Javier F. Pulecio
2011	J	`jnl`	Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays. IEEE Trans. Very Large Scale Integr. Syst. Anita Kumari, Sanjukta Bhanja
2011	J	`jnl`	Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures. IEEE J. Emerg. Sel. Topics Circuits Syst. Jayita Das, Syed M. Alam, Sanjukta Bhanja
2011	J	`jnl`	Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. Microelectron. Reliab. Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
2011	—	`conf`	Novel knowledge module on fusion of logic and memory to undergraduate students. MSE D. K. Karunaratne, Srinath Rajaram, Kristin Kusmierek, Paromita De, Sanjukta Bhanja
2011	C	`conf`	QCAPro - An error-power estimation tool for QCA circuit design. ISCAS Saket Srivastava, Arjun Asthana, Sanjukta Bhanja, Sudeep Sarkar
2009	Misc	`conf`	An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. VLSI Design Karthikeyan Lingasubramanian, Sanjukta Bhanja
2009	—	`conf`	CNT logic knowledge module integrated in digital CMOS logic design course. MSE Anita Kumari, Sanjukta Bhanja
2009	—	`conf`	Defect characterization in magnetic field coupled arrays. ISQED Anita Kumari, Javier F. Pulecio, Sanjukta Bhanja
2009	J	`jnl`	Probabilistic Error Modeling for Nano-Domain Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja
2009	—	`ed.`	Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 ACM Great Lakes Symposium on VLSI Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar
2009	J	`jnl`	Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis CoRR Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
2008	J	`jnl`	Integrating a Nanologic Knowledge Module Into an Undergraduate Logic Design Course. IEEE Trans. Educ. Saket Srivastava, Sanjukta Bhanja
2008	—	`ed.`	Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008 ACM Great Lakes Symposium on VLSI Vijaykrishnan Narayanan, Zhiyuan Yan, Enrico Macii, Sanjukta Bhanja
2008	J	`jnl`	Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits. IEEE Trans. Very Large Scale Integr. Syst. Sanjukta Bhanja, Sudeep Sarkar
2007	J	`jnl`	Hierarchical Probabilistic Macromodeling for QCA Circuits. IEEE Trans. Computers Saket Srivastava, Sanjukta Bhanja
2007	—	`conf`	Integrating Nano-logic into an Undergraduate Logic Design Course. MSE Saket Srivastava, Sanjukta Bhanja
2007	—	`conf`	Probabilistic maximum error modeling for unreliable logic circuits. ACM Great Lakes Symposium on VLSI Karthikeyan Lingasubramanian, Sanjukta Bhanja
2007	J	`jnl`	QCA Circuits for Robust Coplanar Crossing. J. Electron. Test. Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli
2006	Misc	`conf`	A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity. VLSI Design Thara Rejimon, Sanjukta Bhanja
2006	J	`jnl`	A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis. IEEE Trans. Very Large Scale Integr. Syst. Thara Rejimon, Sanjukta Bhanja
2006	J	`jnl`	A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
2006	A	`conf`	Novel designs for thermally robust coplanar crossing in QCA. DATE Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli
2006	Misc	`conf`	Wide Limited Switch Dynamic Logic Circuit Implementations. VLSI Design Thara Rejimon, Sanjukta Bhanja
2005	—	`conf`	A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC. SoCC Vijay K. Jain, Sanjukta Bhanja, Glenn H. Chapman, Lavanya Doddannagari
2005	—	`conf`	A parallel architecture for the ICA algorithm: DSP plane of a 3-D heterogeneous sensor. ICASSP (5) Vijay K. Jain, Sanjukta Bhanja, Glenn H. Chapman, Lavanya Doddannagari, Nguyen Nguyen
2005	Misc	`conf`	An Accurate Probalistic Model for Error Detection. VLSI Design Thara Rejimon, Sanjukta Bhanja
2005	—	`conf`	Causal probabilistic input dependency learning for switching model in VLSI circuits. ACM Great Lakes Symposium on VLSI Nirmal Ramalingam, Sanjukta Bhanja
2005	Misc	`conf`	Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
2004	A	`conf`	Any-time probabilistic switching model using bayesian networks. ISLPED Shiva Shankar Ramani, Sanjukta Bhanja
2004	J	`jnl`	Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. Very Large Scale Integr. Syst. Sanjukta Bhanja, N. Ranganathan
2003	J	`jnl`	Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. Very Large Scale Integr. Syst. Sanjukta Bhanja, N. Ranganathan
2002	C	`conf`	Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. ICCD Sanjukta Bhanja, N. Ranganathan
2002	—	`conf`	Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. ASP-DAC/VLSI Design Sanjukta Bhanja, N. Ranganathan
2001	A*	`conf`	Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. DAC Sanjukta Bhanja, N. Ranganathan
1998	Misc	`conf`	A Qualitative Expert System for Clinical Trial Assignment. FLAIRS Sanjukta Bhanja, Lynn M. Fletcher-Heath, Lawrence O. Hall, Dmitry B. Goldgof, Jeffrey P. Krischer