Sanjay V. Kumar

11 papers A* 2A 3Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2012 A conf
A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations.
ICCAD
Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar
2012 A conf
Circuit reliability: From Physics to Architectures: Embedded tutorial paper.
ICCAD
Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar
2011 J jnl
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2009 — conf
Adaptive techniques for overcoming performance degradation due to aging in digital circuits.
ASP-DAC
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2008 A* conf
A framework for block-based timing sensitivity analysis.
DAC
Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar
2008 J jnl
Body Bias Voltage Computations for Process and Temperature Compensation.
IEEE Trans. Very Large Scale Integr. Syst.
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2008 J jnl
Thermally Aware Design.
Found. Trends Electron. Des. Autom.
Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
2007 A* conf
NBTI-Aware Synthesis of Digital Circuits.
DAC
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006 A conf
An analytical model for negative bias temperature instability.
ICCAD
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006 — conf
Impact of NBTI on SRAM Read Stability and Design for Reliability.
ISQED
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006 — conf
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems.
ASP-DAC
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar