Sani R. Nassif

173 papers A* 20A 38B 3C 12Misc 6Journal 31Unranked 61
YearRankTypeTitle / Venue / Authors
2025 B conf
Analysis and Mitigation of Radiation Effects in SRAM-based Register Files.
ETS
Zhe Zhang, Surendra Hemaram, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2025 — conf
ChatTCAD: Leveraging Large Language Models for Automated TCAD Simulation File Generation.
ISVLSI
Zhe Zhang, Sani R. Nassif, Mehdi B. Tahoori
2025 J jnl
Efficient Deep Neural Network Training With a Novel 5.3-Bit Block Floating Point Data Format.
IEEE Trans. Circuits Syst. Artif. Intell.
Mohammad Hassani Sadi, Chirag Sudarshan, Sani R. Nassif, Norbert Wehn
2025 C conf
Enabling Machine Learning for Power Modeling via Artificial Netlist Generation.
ISCAS
Philipp Fengler, Junpeng Chen, Sani R. Nassif, Ulf Schlichtmann
2025 — conf
Function Approximation Using Analog Building Blocks in Flexible Electronics.
ISQED
Paula Carolina Lozano Duarte, Aradhana Dube, Georgios Zervakis, Mehdi B. Tahoori, Sani R. Nassif
2025 J jnl
Function Approximation Using Analog Building Blocks in Flexible Electronics.
CoRR
Paula Carolina Lozano Duarte, Aradhana Dube, Georgios Zervakis, Mehdi Baradaran Tahoori, Sani R. Nassif
2025 C conf
GDS2SEM: Diffusion-based Layout-to-SEM Post-Fabrication Emulation for IC Validation.
ISCAS
Walaa Amer, Sani R. Nassif, Fadi J. Kurdahi
2025 C conf
Machine Learning for Improving Timing Accuracy.
ISCAS
Mohamed Amine Riahi, Sani R. Nassif, Norbert Wehn
2024 Misc conf
Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management.
VTS
Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2024 A conf
Analog Printed Spiking Neuromorphic Circuit.
DATE
Priyanjana Pal, Haibin Zhao, Maha Shatta, Michael Hefenbrock, Sina Bakhtavari Mamaghani, Sani R. Nassif, Michael Beigl, Mehdi B. Tahoori
2024 C conf
Do Radiation and Aging Impact DVFS? TCAD-based Analysis on 22 nm FDSOI Latches.
IOLTS
Zhe Zhang, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif
2024 — conf
Enabling cell selection optimization for non-traditional CMOS topologies.
ISOCC
André Lucas Chinazzo, Norbert Wehn, Sani R. Nassif
2024 A conf
Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects.
ITC
Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
2024 B conf
Timing Analysis beyond Complementary CMOS Logic Styles.
ASPDAC
Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif
2024 — conf
Timing Analysis with Analytical Sensitivity.
ISOCC
Jan Lappas, Norbert Wehn, Sani R. Nassif
2024 — conf
Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes.
ISQED
Philipp Fengler, Sani R. Nassif, Ulf Schlichtmann
2023 C conf
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication.
VLSI-SoC
Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza
2019 A conf
SRAM Design Exploration with Integrated Application-Aware Aging Analysis.
DATE
Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Sani R. Nassif
2015 J jnl
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures.
IEEE Trans. Very Large Scale Integr. Syst.
Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif
2015 — conf
Analysis and optimization of flip-flops under process and runtime variations.
ISQED
Mohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif
2015 J jnl
Editorial.
IET Comput. Digit. Tech.
Sani R. Nassif, Martin A. Trefzer
2015 J jnl
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool.
IEEE Trans. Very Large Scale Integr. Syst.
Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif
2014 — conf
Applying VLSI EDA to energy distribution system design.
ASP-DAC
Sani R. Nassif, Gi-Joon Nam, Jerry Hayes, Sani Fakhouri
2014 A conf
Connecting different worlds - Technology abstraction for reliability-aware design and Test.
DATE
Ulf Schlichtmann, Veit Kleeberger, Jacob A. Abraham, Adrian Evans, Christina Gimmler-Dumont, Michael Glaß, Andreas Herkersdorf, Sani R. Nassif, Norbert Wehn
2014 — conf
Opportunities in power distribution network system optimization: from EDA perspective.
ISPD
Gi-Joon Nam, Sani R. Nassif
2014 A* conf
Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach.
DAC
Saman Kiamehr, Thomas H. Osiecki, Mehdi Baradaran Tahoori, Sani R. Nassif
2014 J jnl
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab.
Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit Kleeberger, Michael A. Kochte, Johannes Maximilian Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich
2014 A conf
Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations.
ICCAD
Iris Hui-Ru Jiang, Gi-Joon Nam, Hua-Yu Chang, Sani R. Nassif, Jerry Hayes
2014 — conf
Statistical analysis of process variation induced SRAM electromigration degradation.
ISQED
Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif
2013 J jnl
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.
IEEE Micro
Veit Kleeberger, Christina Gimmler-Dumont, Christian Weis, Andreas Herkersdorf, Daniel Mueller-Gritschneder, Sani R. Nassif, Ulf Schlichtmann, Norbert Wehn
2013 B conf
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator.
ETS
Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif
2013 Misc conf
Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo.
ICCS
Thomas H. Osiecki, Min-Yu Tsai, Anne E. Gattiker, Damir A. Jamsek, Sani R. Nassif, William Evan Speight, Cliff C. N. Sze
2013 A conf
ICCAD-2013 CAD contest in mask optimization and benchmark suite.
ICCAD
Shayak Banerjee, Zhuo Li, Sani R. Nassif
2013 — conf
Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.
ESSDERC
Xingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Jente B. Kuang, Sani R. Nassif, Asen Asenov
2013 A conf
Incorporating the impacts of workload-dependent runtime variations into timing analysis.
DATE
Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori, Sani R. Nassif
2013 C conf
Keynote 1 - VLSI 2.0: R&D Post Moore.
VLSI-SoC
Sani R. Nassif, Yale N. Patt, Magdy S. Abadir
2013 J jnl
Layout Decomposition and Legalization for Double-Patterning Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta
2013 A* conf
Reliable on-chip systems in the nano-era: lessons learnt and future trends.
DAC
Jörg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn
2013 — conf
SRAM bit-line electromigration mechanism and its prevention scheme.
ISQED
Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif
2013 C conf
SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.
ISCAS
Binjie Cheng, Xingsheng Wang, Andrew R. Brown, Jente B. Kuang, Dave Reid, Campbell Millar, Sani R. Nassif, Asen Asenov
2013 — conf
Wire delay variability in nanoscale technology and its impact on physical design.
ISQED
Sani R. Nassif, Gi-Joon Nam, Shayak Banerjee
2012 A conf
2012 TAU power grid simulation contest: Benchmark suite and results.
ICCAD
Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif
2012 J jnl
An accurate sparse-matrix based framework for statistical static timing analysis.
Integr.
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan
2012 Misc conf
An oscillation-based test structure for timing information extraction.
VTS
Eun Jung Jang, Anne Gattiker, Sani R. Nassif, Jacob A. Abraham
2012 — conf
Design-aware lithography.
ISPD
Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif
2012 — conf
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction.
ICICDT
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta
2012 — conf
Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues.
ASP-DAC
Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman
2012 A* conf
Yield estimation via multi-cones.
DAC
Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif
2011 A conf
2011 TAU power grid simulation contest: Benchmark suite and results.
ICCAD
Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif
2011 A conf
A framework for double patterning-enabled design.
ICCAD
Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta
2011 A conf
Accelerated statistical simulation via on-demand Hermite spline interpolations.
ICCAD
Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif
2011 — conf
Coupling timing objectives with optical proximity correction for improved timing yield.
ISQED
Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky
2011 Misc conf
Efficient and product-representative timing model validation.
VTS
Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham
2011 — conf
Electrically-driven retargeting for nanoscale layouts.
CICC
Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif
2011 J jnl
Hierarchical Multialgorithm Parallel Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif
2011 — conf
Post-Silicon Timing Validation Method Using Path Delay Measurements.
Asian Test Symposium
Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham
2011 J jnl
Simultaneous Layout Migration and Decomposition for Double Patterning Technology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif
2011 J jnl
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness.
IEEE Trans. Very Large Scale Integr. Syst.
Yun Ye, Frank Liu, Min Chen, Sani R. Nassif, Yu Cao
2011 J jnl
The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Thomas Fröhnel, Sudesh Saroop, Sani R. Nassif, Kevin J. Nowka
2011 J jnl
The Impact of Statistical Leakage Models on Design Yield Estimation.
VLSI Design
Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
2011 C conf
Ultra-low power current-based PUF.
ISCAS
Mehrdad Majzoobi, Golsa Ghiaasi, Farinaz Koushanfar, Sani R. Nassif
2010 J jnl
'Tis the gift to be simple.
IEEE Des. Test Comput.
Sani R. Nassif
2010 — conf
A 32nm 0.5V-supply dual-read 6T SRAM.
CICC
Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka
2010 A conf
A methodology for propagating design tolerances to shape tolerances for use in manufacturing.
DATE
Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky
2010 A conf
A resilience roadmap.
DATE
Sani R. Nassif, Nikil Mehta, Yu Cao
2010 J jnl
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation.
IEEE Trans. Very Large Scale Integr. Syst.
Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao
2010 — conf
Physical design challenges beyond the 22nm node.
ISPD
Sani R. Nassif, Kevin J. Nowka
2010 A conf
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.
ISLPED
Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
2010 A conf
Template-mask design methodology for double patterning technology.
ICCAD
Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif
2010 — conf
The light at the end of the CMOS tunnel.
ASAP
Sani R. Nassif
2009 A conf
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.
ICCAD
Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif
2009 A conf
Analyzing the impact of process variations on parametric measurements: Novel models and applications.
DATE
Sherief Reda, Sani R. Nassif
2009 A conf
Simultaneous layout migration and decomposition for double patterning technology.
ICCAD
Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif
2009 — conf
Statistical yield analysis of silicon-on-insulator embedded DRAM.
ISQED
Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka
2009 — conf
The impact of BEOL lithography effects on the SRAM cell performance and yield.
ISQED
Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi
2009 A conf
Yield estimation of SRAM circuits using "Virtual SRAM Fab".
ICCAD
Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das
2008 A ed.
2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008
ICCAD
Sani R. Nassif, Jaijeet S. Roychowdhury
2008 — conf
A Design Model for Random Process Variability.
ISQED
Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic
2008 — conf
A Root-Finding Method for Assessing SRAM Stability.
ISQED
Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif
2008 — conf
Analytical model for the impact of multiple input switching noise on timing.
ASP-DAC
Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham
2008 — conf
Characterization and design for variability and reliability.
CICC
Kevin J. Nowka, Sani R. Nassif, Kanak Agarwal
2008 Misc conf
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.
VLSI Design
Fadi J. Kurdahi, Nikil D. Dutt, Ahmed M. Eltawil, Sani R. Nassif
2008 A conf
Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level.
DATE
Diana Marculescu, Sani R. Nassif
2008 — book
Design for Manufacturability and Statistical Design - A Constructive Approach.
Michael Orshansky, Sani R. Nassif, Duane S. Boning
2008 A conf
MAPS: multi-algorithm parallel circuit simulation.
ICCAD
Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif
2008 — conf
Model to Hardware Matching for nm Scale Technologies.
PATMOS
Sani R. Nassif
2008 — ch.
Power Grid Design.
Handbook of Algorithms for Physical Design Automation
Haihua Su, Sani R. Nassif
2008 — conf
Power grid analysis benchmarks.
ASP-DAC
Sani R. Nassif
2008 — conf
Process variability at the 65nm node and beyond.
CICC
Sani R. Nassif
2008 A conf
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
ISLPED
Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif
2008 — conf
Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.
ISQED
Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif
2008 A* conf
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.
DAC
Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao
2008 — conf
Technology modeling and characterization beyond the 45nm node.
ASP-DAC
Sani R. Nassif
2008 J jnl
The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst.
Kanak Agarwal, Sani R. Nassif
2007 A* conf
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.
DAC
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
2007 A* conf
Characterizing Process Variation in Nanometer CMOS.
DAC
Kanak Agarwal, Sani R. Nassif
2007 — conf
Estimating path delay distribution considering coupling noise.
ACM Great Lakes Symposium on VLSI
Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham
2007 — conf
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.
ISQED
Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif
2007 — conf
Model to Hardware matching for nano-meter scale technologies.
ESSCIRC
Sani R. Nassif
2007 J jnl
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
CoRR
Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
2007 A* conf
Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.
DAC
Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao
2007 — conf
Rigorous extraction of process variations for 65nm CMOS design.
ESSCIRC
Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka
2006 — conf
Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity.
ISQED
Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif
2006 A conf
An accurate sparse matrix based framework for statistical static timing analysis.
ICCAD
Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
2006 A conf
Analytical modeling of SRAM dynamic stability.
ICCAD
Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky
2006 C conf
Characterization of total chip leakage using inverse (reciprocal) gamma distribution.
ISCAS
Emrah Acar, Kanak Agarwal, Sani R. Nassif
2006 — conf
Circuit Optimization Using Scale Based Sensitivities.
CICC
Bhavna Agrawal, Frank Liu, Sani R. Nassif
2006 J jnl
Guest Editors' Introduction: Process Variation and Stochastic Design and Test.
IEEE Des. Test Comput.
T. M. Mak, Sani R. Nassif
2006 J jnl
High-performance CMOS variability in the 65-nm regime and beyond.
IBM J. Res. Dev.
Kerry Bernstein, David J. Frank, Anne E. Gattiker, Wilfried Haensch, Brian L. Ji, Sani R. Nassif, Edward J. Nowak, Dale J. Pearson, Norman J. Rohrer
2006 C conf
Methods for estimating decoupling capacitance of nonswitching circuit blocks.
ISCAS
Sani R. Nassif, Kanak Agarwal, Emrah Acar
2006 A* conf
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.
DAC
Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
2006 A conf
Model to hardware matching: for nano-meter scale technologies.
ISLPED
Sani R. Nassif
2006 — conf
SRAM Local Bit Line Access Failure Analyses.
ISQED
Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif
2006 A* conf
Statistical analysis of SRAM cell stability.
DAC
Kanak Agarwal, Sani R. Nassif
2006 — conf
System-Level SRAM Yield Enhancement.
ISQED
Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif
2006 A* conf
Variation-aware analysis: savior of the nanometer era?
DAC
Sani R. Nassif, Vijay Pitchumani, Norma Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic
2005 — conf
A More Effective C
ISQED
Sani R. Nassif, Zhuo Li
2005 — conf
An efficient surface-based low-power buffer insertion algorithm.
ISPD
Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
2005 C conf
Benefits and Costs of Power-Gating Technique.
ICCD
Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
2005 J jnl
Early-stage power grid analysis for uncertain working modes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
2005 J jnl
Leakage and Leakage Sensitivity Computation for Combinational Circuits.
J. Low Power Electron.
Emrah Acar, Anirudh Devgan, Sani R. Nassif
2005 A conf
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.
DATE
Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
2005 Misc conf
Power Variability and Its Impact on Design.
VLSI Design
Anirudh Devgan, Sani R. Nassif
2005 J jnl
Power grid analysis using random walks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
2005 — conf
Power-aware global signaling strategies.
ISCAS (1)
Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
2005 A conf
Testing and debugging delay faults in dynamic circuits.
ITC
Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham
2005 A* conf
The Titanic: what went wrong!
DAC
Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse
2004 A conf
A chip-level electrostatic discharge simulation strategy.
ICCAD
Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar
2004 J jnl
A methodology for the simultaneous design of supply and signal networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
2004 A conf
Approaches to run-time and standby mode leakage reduction in global buses.
ISLPED
Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
2004 — conf
Early-stage power grid analysis for uncertain working modes.
ISPD
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
2004 J jnl
Impact of Design-Manufacturing Interface on SoC Design Methodologies.
IEEE Des. Test Comput.
Juan Antonio Carballo, Sani R. Nassif
2004 A conf
The care and feeding of your statistical static timer.
ICCAD
Sani R. Nassif, Duane S. Boning, Nagib Hakim
2004 A conf
The impact of variability on power.
ISLPED
Sani R. Nassif
2004 A* conf
Variational delay metrics for interconnect timing analysis.
DAC
Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula
2003 A conf
Full chip leakage estimation considering power supply and temperature variations.
ISLPED
Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif
2003 J jnl
Guest Editors' Introduction: On-Chip Power Distribution Networks.
IEEE Des. Test Comput.
Sani R. Nassif, Soha Hassoun
2003 A conf
Leakage and leakage sensitivity computation for combinational circuits.
ISLPED
Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
2003 J jnl
Optimal decoupling capacitor sizing and placement for standard-cell layout designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
2003 — conf
Optimal shielding/spacing metrics for low power design.
ISVLSI
Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif
2003 A* conf
Power grid reduction based on algebraic multigrid principles.
DAC
Haihua Su, Emrah Acar, Sani R. Nassif
2003 — conf
Predicting short circuit power from timing models.
ASP-DAC
Emrah Acar, Ravishankar Arunachalam, Sani R. Nassif
2003 A* conf
Random walks in a supply network.
DAC
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
2002 A conf
A Linear-Centric Simulation Framework for Parametric Fluctuations.
DATE
Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi
2002 J jnl
A multigrid-like technique for power grid analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
2002 — conf
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.
ISPD
Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif
2002 A* conf
Congestion-driven codesign of power and signal networks.
DAC
Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif
2002 — conf
Impact of Technology in Power-Grid-Induced Noise.
PATMOS
Juan Antonio Carballo, Sani R. Nassif
2002 — conf
Static timing analysis based circuit-limited-yield estimation.
ISCAS (5)
Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
2002 — conf
Technology trends in power-grid-induced noise.
SLIP
Sani R. Nassif, Onsi Fakhouri
2002 — conf
Test structures for delay variability.
Timing Issues in the Specification and Synthesis of Digital Systems
Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu
2002 — conf
Time-Domain Simulation of Variational Interconnect Models.
ISQED
Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi
2001 — conf
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.
ISQED
Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu
2001 — conf
Beyond the red brick wall (panel): challenges and solutions in 50nm physical design.
ASP-DAC
Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori
2001 — conf
I/O buffer placement methodology for ASICs.
ICECS
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
2001 — conf
Modeling and analysis of manufacturing variations.
CICC
Sani R. Nassif
2001 — conf
Modeling and forecasting of manufacturing variations (embedded tutorial).
ASP-DAC
Sani R. Nassif
2001 A conf
Multigrid-Like Technique for Power Grid Analysis.
ICCAD
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
2001 — conf
Timing Yield Estimation from Static Timing Analysis.
ISQED
Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long
2000 A* conf
A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance.
DAC
Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif
2000 — conf
Design for Variability in DSM Technologies.
ISQED
Sani R. Nassif
2000 A conf
Designing Closer to the Edge.
DATE
Sani R. Nassif
2000 A* conf
Fast power grid simulation.
DAC
Sani R. Nassif, Joseph N. Kozhaya
2000 A* conf
Impact of interconnect variations on the clock skew of a gigahertz microprocessor.
DAC
Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas
2000 C conf
Multi-grid methods for power grid simulation.
ISCAS
Sani R. Nassif, Joseph N. Kozhaya
2000 A* conf
When bad things happen to good chips (panel session).
DAC
N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang
1999 A conf
SOI technology and tools (abstract).
ICCAD
Sani R. Nassif, Tuyen V. Nguyen
1998 — conf
IR and Thermal Estimation Tools, with Applications to the GUTS 1GHz Processor.
SBCCI
A. Carvalho, Fadi J. Kurdahi, Sani R. Nassif
1997 — conf
Physical design challenges for performance.
ISPD
David P. LaPotin, Uttam Ghoshal, Eli Chiprout, Sani R. Nassif
1986 J jnl
A Methodology for Worst-Case Analysis of Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
1986 A* conf
CINNAMON: coupled integration and nodal analysis of MOS networks.
DAC
Luís M. Vidigal, Sani R. Nassif, Stephen W. Director
1984 J jnl
DIF: A framework for VLSI multi-level representation.
Integr.
David P. LaPotin, Sani R. Nassif, Jayanth V. Rajan, Michael L. Bushnell, John A. Nestor
1984 J jnl
FABRICS II: A Statistically Based IC Fabrication Process Simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director