Sangyeob Kim

76 papers C 6Journal 31Unranked 39
YearRankTypeTitle / Venue / Authors
2026 J jnl
EdgeDiff: Energy-Efficient Multi-Modal Few-Step Diffusion Model Accelerator Using Mixed-Precision and Reordered Group Quantization.
IEEE J. Solid State Circuits
Sangjin Kim, Jungjun Oh, Jeonggyu So, Yuseon Choi, Sangyeob Kim, Dongseok Im, Gwangtae Park, Hoi-Jun Yoo
2026 J jnl
FlashMoE: Reducing SSD I/O Bottlenecks via ML-Based Cache Replacement for Mixture-of-Experts Inference on Edge Devices.
CoRR
Byeongju Kim, Jungwan Lee, Donghyeon Han, Hoi-Jun Yoo, Sangyeob Kim
2025 — conf
23.3 EdgeDiff: 418.4mJ/Inference Multi-Modal Few-Step Diffusion Model Accelerator with Mixed-Precision and Reordered Group Quantization.
ISSCC
Sangjin Kim, Jungjun Oh, Jeonggyu So, Yuseon Choi, Sangyeob Kim, Dongseok Im, Gwangtae Park, Hoi-Jun Yoo
2025 — conf
23.7 BROCA: A 52.4-to-559.2mW Mobile Social Agent System-on-Chip with Adaptive Bit-Truncate Unit and Acoustic-Cluster Bit Grouping.
ISSCC
Wooyoung Jo, Seongyon Hong, Jiwon Choi, Beomseok Kwon, Haoyang Sang, Dongseok Im, Sangyeob Kim, Sangjin Kim, Taekwon Lee, Hoi-Jun Yoo
2025 — conf
A 4.69mW LLM Processor with Binary/Ternary Weights for Billion-Parameter Llama Model.
HCS
Sangyeob Kim, Jungwan Lee, Byeongju Kim, Hoi-Jun Yoo
2025 C conf
A 65.1 TOPS/W Digital CIM Processor for Ultra-Low-Bit Transformers with Multiplexer-based Adder and Scaling Factor-based Reordering.
ISCAS
Nayeong Lee, Sangyeob Kim, Seongyon Hong, Jiwon Choi, Hoi-Jun Yoo
2025 — conf
BROCA: A Low-power and Low-latency Conversational Agent RISC-V System-on-Chip for Voice-interactive Mobile Devices.
HCS
Wooyoung Jo, Seongyon Hong, Jiwon Choi, Beomseok Kwon, Haoyang Sang, Dongseok Im, Sangyeob Kim, Sangjin Kim, Chaeyun Jeong, Yujin Moon, Hoi-Jun Yoo
2025 J jnl
C-Transformer: An Energy-Efficient Homogeneous DNN-Transformer/SNN-Transformer Processor for Large Language Models.
IEEE J. Solid State Circuits
Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, Nayeong Lee, Jungwan Lee, Hoi-Jun Yoo
2025 J jnl
Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI.
IEEE J. Solid State Circuits
Seongyon Hong, Wooyoung Jo, Sangjin Kim, Sangyeob Kim, Soyeon Um, Kyomin Sohn, Hoi-Jun Yoo
2025 J jnl
ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM.
IEEE J. Solid State Circuits
Wenao Xie, Haoyang Sang, Beomseok Kwon, Dongseok Im, Sangjin Kim, Sangyeob Kim, Kangho Lee, Hoi-Jun Yoo
2025 — conf
EdgeDiff: Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization for On-device Generative AI Motivation.
HCS
Sangjin Kim, Jungjun Oh, Jeonggyu So, Yuseon Choi, Sangyeob Kim, Dongseo Kim, Gwangtae Park, Hoi-Jun Yoo
2025 J jnl
NeRF-Navi: An Energy-Efficient NeRF 3-D Path Planning Processor With Reconfigurable Approximate/Accurate Bit Offloading Core.
IEEE J. Solid State Circuits
Seryeong Kim, Seokchan Song, Wonhoon Park, Junha Ryu, Gwangtae Park, Sangyeob Kim, Soyeon Kim, Donghyeon Han, Hoi-Jun Yoo
2025 J jnl
NeuGPU: An Energy-Efficient Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile Devices.
IEEE J. Solid State Circuits
Junha Ryu, Hankyul Kwon, Wonhoon Park, Zhiyong Li, Beomseok Kwon, Donghyeon Han, Dongseok Im, Sangyeob Kim, Hyungnam Joo, Minsung Kim, Hoi-Jun Yoo
2025 — conf
Slim-Llama: A 4.69mW Large-Language-Model Processor with Binary/Ternary Weights for Billion-Parameter Llama Model.
ISSCC
Sangyeob Kim, Jungwan Lee, Hoi-Jun Yoo
2024 — conf
20.5 C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models.
ISSCC
Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, Hoi-Jun Yoo
2024 — conf
20.7 NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with Segmented-Hashing Architecture.
ISSCC
Junha Ryu, Hankyul Kwon, Wonhoon Park, Zhiyong Li, Beomseok Kwon, Donghyeon Han, Dongseok Im, Sangyeob Kim, Hyungnam Joo, Hoi-Jun Yoo
2024 — conf
20.8 Space-Mate: A 303.5mW Real-Time Sparse Mixture-of-Experts-Based NeRF-SLAM Processor for Mobile Spatial Computing.
ISSCC
Gwangtae Park, Seokchan Song, Haoyang Sang, Dongseok Im, Donghyeon Han, Sangyeob Kim, Hongseok Lee, Hoi-Jun Yoo
2024 J jnl
A Low-Power Artificial-Intelligence-Based 3-D Rendering Processor With Hybrid Deep Neural Network Computing.
IEEE Micro
Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo
2024 — conf
A Low-Power Large-Language-Model Processor with Big-Little Network and Implicit-Weight-Generation for On-Device AI.
HCS
Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Soyeon Kim, Seongyon Hong, Nayeong Lee, Hoi-Jun Yoo
2024 — conf
A Low-Power Neural Graphics System for Instant 3D Modeling and Real-Time Rendering on Mobile AR/VR Devices.
COOL CHIPS
Junha Ryu, Hankyul Kwon, Wonhoon Park, Zhiyong Li, Beomseok Kwon, Donghyeon Han, Dongseok Im, Sangyeob Kim, Hyungnam Joo, Minsung Kim, Hoi-Jun Yoo
2024 — conf
A Low-power and Real-time Neural-Rendering Dense SLAM Processor with 3-Level Hierarchical Sparsity Exploitation.
COOL CHIPS
Gwangtae Park, Seokchan Song, Haoyang Sang, Dongseok Im, Donghyeon Han, Sangyeob Kim, Hongseok Lee, Hoi-Jun Yoo
2024 J jnl
An Artificial-Intelligence-Based SLAM Processor With Scene-Adaptive Sampling and Hybrid NeRF Model Training Acceleration.
IEEE Trans. Circuits Syst. Artif. Intell.
Gwangtae Park, Seokchan Song, Haoyang Sang, Dongseok Im, Donghyeon Han, Sangyeob Kim, Hongseok Lee, Hoi-Jun Yoo
2024 J jnl
C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN Core Architecture.
IEEE J. Solid State Circuits
Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Jiwon Choi, Hoi-Jun Yoo
2024 J jnl
COOL-NPU: Complementary Online Learning Neural Processing Unit.
IEEE Micro
Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Jiwon Choi, Donghyeon Han, Hoi-Jun Yoo
2024 — conf
DualNet: Efficient Integration of Artificial Neural Network and Spiking Neural Network with Equivalent Conversion.
AICAS
Seongyon Hong, Sangyeob Kim, Soyeon Kim, Hoi-Jun Yoo
2024 — conf
Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow.
VLSI Technology and Circuits
Seongyon Hong, Wooyoung Jo, Sangjin Kim, Sangyeob Kim, Kyomin Sohn, Hoi-Jun Yoo
2024 J jnl
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell.
IEEE J. Solid State Circuits
Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo
2024 J jnl
Improved climate time series forecasts by machine learning and statistical models coupled with signature method: A case study with El Niño.
Ecol. Informatics
Jonathan Derot, Nozomi Sugiura, Sangyeob Kim, Shinya Kouketsu
2024 J jnl
LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell.
IEEE J. Solid State Circuits
Soyeon Um, Sangjin Kim, Seongyon Hong, Sangyeob Kim, Hoi-Jun Yoo
2024 J jnl
MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing.
IEEE J. Solid State Circuits
Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo
2024 — conf
NeRF-Navi: A 93.6-202.9µJ/task Switchable Approximate-Accurate NeRF Path Planning Processor with Dual Attention Engine and Outlier Bit-Offloading Core.
VLSI Technology and Circuits
Seryeong Kim, Seokchan Song, Wonhoon Park, Junha Ryu, Sangyeob Kim, Gwangtae Park, Soyeon Kim, Hoi-Jun Yoo
2024 — conf
NeuGPU: A Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile AR/VR Devices.
HCS
Junha Ryu, Hankyul Kwon, Wonhoon Park, Zhiyong Li, Beomseok Kwon, Donghyeon Han, Dongseok Im, Sangyeob Kim, Hyungnam Joo, Minsung Kim, Hoi-Jun Yoo
2024 — conf
NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator.
COOL CHIPS
Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Sangyeob Kim, Hoi-Jun Yoo
2024 — conf
Space-Mate: A 303.5mW Real-Time NeRF SLAM Processor with Sparse-Mixture-of-Experts-based Acceleration.
HCS
Seokchan Song, Haoyang Sang, Dongseok Im, Donghyeon Han, Sangyeob Kim, Hongseok Lee, Hoi-Jun Yoo
2024 C conf
Two-Step Spike Encoding Scheme and Architecture for Highly Sparse Spiking-Neural-Network.
ISCAS
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Hoi-Jun Yoo
2023 C conf
A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC.
ISCAS
Seongyon Hong, Soyeon Um, Sangjin Kim, Sangyeob Kim, Wooyoung Jo, Hoi-Jun Yoo
2023 — conf
A 709.3 TOPS/W Event-Driven Smart Vision SoC with High-Linearity and Reconfigurable MRAM PIM.
VLSI Technology and Circuits
Wenao Xie, Haoyang Sang, Beomseok Kwon, Dongseok Im, Sangjin Kim, Sangyeob Kim, Hoi-Jun Yoo
2023 — conf
A Low-power Neural 3D Rendering Processor with Bio-inspired Visual Perception Core and Hybrid DNN Acceleration.
COOL CHIPS
Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo
2023 C conf
A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency.
ISCAS
Seryeong Kim, Soyeon Kim, Soyeon Um, Sangjin Kim, Zhiyong Li, Sangyeob Kim, Wooyoung Jo, Hoi-Jun Yoo
2023 — conf
A Resource-Efficient Super-Resolution FPGA Processor with Heterogeneous CNN and SNN Core Architecture.
A-SSCC
Jiwon Choi, Sangyeob Kim, Wonhoon Park, Wooyoung Jo, Hoi-Jun Yoo
2023 J jnl
C-DNN V2: Complementary Deep-Neural-Network Processor With Full-Adder/OR-Based Reduction Tree and Reconfigurable Spatial Weight Reuse.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Sangyeob Kim, Hoi-Jun Yoo
2023 — conf
C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation.
ISSCC
Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Hoi-Jun Yoo
2023 — conf
COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation.
COOL CHIPS
Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Jiwon Choi, Hoi-Jun Yoo
2023 — conf
DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching.
ISSCC
Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo
2023 — conf
GPPU: A 330.4-μJ/ task Neural Path Planning Processor with Hybrid GNN Acceleration for Autonomous 3D Navigation.
VLSI Technology and Circuits
Seokchan Song, Donghyeon Han, Sangjin Kim, Sangyeob Kim, Gwangtae Park, Hoi-Jun Yoo
2023 — conf
LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell.
A-SSCC
Soyeon Um, Sangjin Kim, Seongyon Hong, Sangyeob Kim, Hoi-Jun Yoo
2023 — conf
MetaVRain: A 133mW Real-Time Hyper-Realistic 3D-NeRF Processor with 1D-2D Hybrid-Neural Engines for Metaverse on Mobile Devices.
ISSCC
Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
2023 — conf
NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices.
VLSI Technology and Circuits
Wooyoung Jo, Sangjin Kim, Juhyoung Lee, Donghyeon Han, Sangyeob Kim, Seungyoon Choi, Hoi-Jun Yoo
2023 J jnl
Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital-Analog Networks.
IEEE J. Solid State Circuits
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, Hoi-Jun Yoo
2023 J jnl
SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit.
IEEE J. Solid State Circuits
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Juhyoung Lee, Hoi-Jun Yoo
2022 J jnl
A Low-Power Graph Convolutional Network Processor With Sparse Grouping for 3D Point Cloud Semantic Segmentation in Mobile Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sangjin Kim, Sangyeob Kim, Juhyoung Lee, Hoi-Jun Yoo
2022 J jnl
Design of Sub-10-μW Sub-0.1% THD Sinusoidal Current Generator IC for Bio-Impedance Sensing.
IEEE J. Solid State Circuits
Kwantae Kim, Sangyeob Kim, Hoi-Jun Yoo
2022 J jnl
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor.
IEEE Micro
Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
2022 — conf
Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing.
HCS
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, Hoi-Jun Yoo
2022 — conf
Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing.
VLSI Technology and Circuits
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, Hoi-Jun Yoo
2022 J jnl
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer.
IEEE J. Solid State Circuits
Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Ji-Hoon Kim, Donghyeon Han, Hoi-Jun Yoo
2022 J jnl
TSUNAMI: Triple Sparsity-Aware Ultra Energy-Efficient Neural Network Training Accelerator With Multi-Modal Iterative Pruning.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Donghyeon Han, Wooyoung Jo, Hoi-Jun Yoo
2022 J jnl
Two-Step Spike Encoding Scheme and Architecture for Highly Sparse Spiking-Neural-Network.
CoRR
Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Hoi-Jun Yoo
2021 — conf
A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory.
VLSI Circuits
Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Jinsu Lee, Hoi-Jun Yoo
2021 J jnl
A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory With Computation Reuse.
IEEE Trans. Circuits Syst. II Express Briefs
Soyeon Um, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
2021 J jnl
A 64.1mW Accurate Real-Time Visual Object Tracking Processor With Spatial Early Stopping on Siamese Network.
IEEE Trans. Circuits Syst. II Express Briefs
Soyeon Kim, Sangjin Kim, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo
2021 J jnl
An Energy-Efficient GAN Accelerator With On-Chip Training for Domain-Specific Optimization.
IEEE J. Solid State Circuits
Soyeon Kim, Sanghoon Kang, Donghyeon Han, Sangjin Kim, Sangyeob Kim, Hoi-Jun Yoo
2021 — conf
An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory.
HCS
Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Donghyeon Han, Jinsu Lee, Hoi-Jun Yoo
2021 — conf
Energy-Efficient Deep Reinforcement Learning Accelerator Designs for Mobile Autonomous Systems.
AICAS
Juhyoung Lee, Changhyeon Kim, Donghyeon Han, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
2021 J jnl
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation.
IEEE J. Solid State Circuits
Sanghoon Kang, Donghyeon Han, Juhyoung Lee, Dongseok Im, Sangyeob Kim, Soyeon Kim, Junha Ryu, Hoi-Jun Yoo
2021 J jnl
GST: Group-Sparse Training for Accelerating Deep Reinforcement Learning.
CoRR
Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Hoi-Jun Yoo
2021 — conf
OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer.
VLSI Circuits
Juhyoung Lee, Sangyeob Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Jinsu Lee, Hoi-Jun Yoo
2021 — conf
OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data.
HCS
Juhyoung Lee, Sangyeob Kim, Ji-Hoon Kim, Sangjin Kim, Wooyoung Jo, Donghyeon Han, Hoi-Jun Yoo
2020 — conf
7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation.
ISSCC
Sanghoon Kang, Donghyeon Han, Juhyoung Lee, Dongseok Im, Sangyeob Kim, Soyeon Kim, Hoi-Jun Yoo
2020 — conf
A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping.
VLSI Circuits
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinmook Lee, Hoi-Jun Yoo
2020 C conf
A 54.7 fps 3D Point Cloud Semantic Segmentation Processor with Sparse Grouping Based Dilated Graph Convolutional Network for Mobile Devices.
ISCAS
Sangjin Kim, Sangyeob Kim, Juhyoung Lee, Hoi-Jun Yoo
2020 J jnl
A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinsu Lee, Hoi-Jun Yoo
2020 — conf
An Energy-Efficient GAN Accelerator with On-chip Training for Domain Specific Optimization.
A-SSCC
Soyeon Kim, Sanghoon Kang, Donghyeon Han, Sangyeob Kim, Sangjin Kim, Hoi-Jun Yoo
2019 C conf
A 15.2 TOPS/W CNN Accelerator with Similar Feature Skipping for Face Recognition in Mobile Devices.
ISCAS
Sangyeob Kim, Juhyoung Lee, Sanghoon Kang, Jinsu Lee, Hoi-Jun Yoo
2019 J jnl
UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision.
IEEE J. Solid State Circuits
Jinmook Lee, Changhyeon Kim, Sanghoon Kang, Dongjoo Shin, Sangyeob Kim, Hoi-Jun Yoo
2018 — conf
UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision.
ISSCC
Jinmook Lee, Changhyeon Kim, Sanghoon Kang, Dongjoo Shin, Sangyeob Kim, Hoi-Jun Yoo