Sangjin Byun

23 papers C 1Journal 19Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
Analysis and Design of an 884-MHz Duty-Cycled Ambient RF Energy Harvester IC Capturing 8.7 μJ From -35.2 dBm per 1.6 Hours.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yoomi Park, Hyeonsoo Seung, Sangjin Byun
2025 J jnl
On Using nMOS-pMOS-Type Cells in a Threshold-Voltage Compensated CMOS RF-DC Rectifier.
IEEE Trans. Very Large Scale Integr. Syst.
Yoomi Park, Sangjin Byun
2024 C conf
An 884MHz, -41.8dBm Input Power Sensitivity, 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors.
ISCAS
Yoomi Park, Sangjin Byun
2024 J jnl
Analysis and Design of a 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yoomi Park, Sangjin Byun
2020 J jnl
A Poly Resistor Based Time Domain CMOS Temperature Sensor with 9b SAR and Fine Delay Line.
Sensors
Zhiwei Xu, Sangjin Byun
2020 J jnl
Categorization and Characterization of Time Domain CMOS Temperature Sensors.
Sensors
Sangjin Byun
2017 J jnl
Analysis and Verification of DLL-Based GFSK Demodulator Using Multiple-IF-Period Delay Line.
IEEE Trans. Circuits Syst. II Express Briefs
Sangjin Byun
2017 J jnl
On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors.
IEEE Trans. Circuits Syst. II Express Briefs
Chung Hwan Son, Sangjin Byun
2016 J jnl
0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling.
IET Circuits Devices Syst.
Sangjin Byun
2016 J jnl
1∼3 GHz VCO with rail-to-rail V
IEICE Electron. Express
Sangjin Byun
2016 J jnl
A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sangjin Byun
2014 J jnl
Analysis and Design of CMOS Received Signal Strength Indicator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sangjin Byun
2013 J jnl
1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector.
IET Circuits Devices Syst.
Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu
2012 J jnl
Simple odd number frequency divider with 50% duty cycle.
IEICE Electron. Express
Sangjin Byun, Chung Hwan Son, Jae Joon Kim
2011 J jnl
A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications.
IEICE Electron. Express
Jae Joon Kim, Chang-Hyuk Cho, Kwan-Yeob Chae, Sangjin Byun
2010 J jnl
Charge Pump circuit with wide range digital leakage current mismatch compensator.
IEICE Electron. Express
Sangjin Byun, Jae Hoon Shim
2008 J jnl
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology.
IEEE J. Solid State Circuits
Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu
2006 J jnl
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector.
IEEE J. Solid State Circuits
Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu
2006 — conf
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector.
ISSCC
Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu
2006 — conf
A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS.
ISSCC
Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu
2005 J jnl
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer.
IEEE J. Solid State Circuits
Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. Conroy, Beomsup Kim
2003 J jnl
A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator.
IEEE J. Solid State Circuits
Sangjin Byun, Chan-Hong Park, Yongchul Song, Sung-Ho Wang, Cormac S. G. Conroy, Beomsup Kim
1999 — conf
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony.
ASP-DAC
Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sangjin Byun, Bae Sung Kwon, Beomsup Kim