Sanghamitra Roy

89 papers A* 14A 16B 1C 7Misc 3Journal 35Unranked 12

Year	Rank	Type	Title / Venue / Authors
2026	B	`conf`	Probabilistic Verification for Modular Network-on-Chip Systems. VMCAI Nick Waddoups, Jonah Boe, Arnd Hartmanns, Prabal Basu, Sanghamitra Roy, Koushik Chakraborty, Zhen Zhang
2025	J	`jnl`	Probabilistic Verification for Modular Network-on-Chip Systems (extended version). CoRR Nick Waddoups, Jonah Boe, Arnd Hartmanns, Prabal Basu, Sanghamitra Roy, Koushik Chakraborty, Zhen Zhang
2025	J	`jnl`	STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience. ACM Trans. Design Autom. Electr. Syst. Noel Daniel Gundi, Sanghamitra Roy, Koushik Chakraborty
2023	A*	`conf`	STRIVE: Enabling Choke Point Detection and Timing Error Resilience in a Low-Power Tensor Processing Unit. DAC Noel Daniel Gundi, Zinnia Muntaha Mowri, Andrew Chamberlin, Sanghamitra Roy, Koushik Chakraborty
2021	J	`jnl`	EFFORT: A Comprehensive Technique to Tackle Timing Violations and Improve Energy Efficiency of Near-Threshold Tensor Processing Units. IEEE Trans. Very Large Scale Integr. Syst. Noel Daniel Gundi, Tahmoures Shabanian, Prabal Basu, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty
2021	C	`conf`	Probabilistic Verification for Reliability of a Two-by-Two Network-on-Chip System. FMICS Riley Roberts, Benjamin Lewis, Arnd Hartmanns, Prabal Basu, Sanghamitra Roy, Koushik Chakraborty, Zhen Zhang
2021	J	`jnl`	Probabilistic Verification for Reliability of a Two-by-Two Network-on-Chip System. CoRR Riley Roberts, Benjamin Lewis, Arnd Hartmanns, Prabal Basu, Sanghamitra Roy, Koushik Chakraborty, Zhen Zhang
2021	A*	`conf`	UPTPU: Improving Energy Efficiency of a Tensor Processing Unit through Underutilization Based Power-Gating. DAC Pramesh Pandey, Noel Daniel Gundi, Koushik Chakraborty, Sanghamitra Roy
2021	J	`jnl`	Understanding Security Threats in Emerging Neuromorphic Computing Architecture. J. Hardw. Syst. Secur. Chidhambaranathan Rajamanikkam, Rajesh J. S., Sanghamitra Roy, Koushik Chakraborty
2021	J	`jnl`	Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform. CoRR Rourab Paul, Sreetama Sarkar, Suman Sau, Koushik Chakraborty, Sanghamitra Roy, Amlan Chakrabarti
2020	—	`conf`	EFFORT: Enhancing Energy Efficiency and Error Resilience of a Near-Threshold Tensor Processing Unit. ASP-DAC Noel Daniel Gundi, Tahmoures Shabanian, Prabal Basu, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty, Zhen Zhang
2020	J	`jnl`	Exploring Warp Criticality in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis. IEEE Trans. Very Large Scale Integr. Syst. Sourav Sanyal, Prabal Basu, Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty
2020	J	`jnl`	GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit. IEEE Trans. Very Large Scale Integr. Syst. Pramesh Pandey, Prabal Basu, Koushik Chakraborty, Sanghamitra Roy
2020	J	`jnl`	TITAN: Uncovering the Paradigm Shift in Security Vulnerability at Near-Threshold Computing. IEEE Trans. Emerg. Top. Comput. Prabal Basu, Pramesh Pandey, Aatreyi Bal, Chidhambaranathan Rajamanikkam, Koushik Chakraborty, Sanghamitra Roy
2019	J	`jnl`	Energy Efficient Network-on-Chip Architectures for Many-Core Near-Threshold Computing System. J. Low Power Electron. Chidhambaranathan Rajamanikkam, Rajesh J. S., Koushik Chakraborty, Sanghamitra Roy
2019	A*	`conf`	GreenTPU: Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit. DAC Pramesh Pandey, Prabal Basu, Koushik Chakraborty, Sanghamitra Roy
2019	A	`conf`	Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis. DATE Sourav Sanyal, Prabal Basu, Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty
2019	C	`conf`	Probabilistic Verification for Reliable Network-on-Chip System Design. FMICS Benjamin Lewis, Arnd Hartmanns, Prabal Basu, Rajesh Jayashankara Shridevi, Koushik Chakraborty, Sanghamitra Roy, Zhen Zhang
2019	J	`jnl`	Securing Data Center Against Power Attacks. J. Hardw. Syst. Secur. Rajesh J. S., Chidhambaranathan Rajamanikkam, Koushik Chakraborty, Sanghamitra Roy
2018	A	`conf`	ACE-GPU: Tackling Choke Point Induced Performance Bottlenecks in a Near-Threshold Computing GPU. ISLPED Tahmoures Shabanian, Aatreyi Bal, Prabal Basu, Koushik Chakraborty, Sanghamitra Roy
2018	J	`jnl`	Dynamic Choke Sensing for Timing Error Resilience in NTC Systems. IEEE Trans. Very Large Scale Integr. Syst. Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty
2018	J	`jnl`	FIFA: Exploring a Focally Induced Fault Attack Strategy in Near-Threshold Computing. IEEE Embed. Syst. Lett. Prabal Basu, Chidhambaranathan Rajamanikkam, Aatreyi Bal, Pramesh Pandey, Trevor Carter, Koushik Chakraborty, Sanghamitra Roy
2018	A	`conf`	Reliability and Uniformity Enhancement in 8T-SRAM based PUFs operating at NTC. ISLPED Pramesh Pandey, Asmita Pal, Koushik Chakraborty, Sanghamitra Roy
2018	J	`jnl`	TASPDetect: Reviving Trust in 3PIP By Detecting TASP Trojans. Microprocess. Microsystems Chidhambaranathan Rajamanikkam, Kurt Brenning, Andrew Deakin, Sanghamitra Roy, Koushik Chakraborty
2018	A	`conf`	Trident: A comprehensive timing error resilient technique against choke points at NTC. DATE Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty
2018	J	`jnl`	Trident: Comprehensive Choke Error Mitigation in NTC Systems. IEEE Trans. Very Large Scale Integr. Syst. Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty
2017	J	`jnl`	IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms. IEEE Trans. Very Large Scale Integr. Syst. Prabal Basu, Rajesh Jayashankara Shridevi, Koushik Chakraborty, Sanghamitra Roy
2017	A	`conf`	Revamping timing error resilience to tackle choke points at NTC systems. DATE Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty
2017	J	`jnl`	SSAGA: SMs Synthesized for Asymmetric GPGPU Applications. ACM Trans. Design Autom. Electr. Syst. Shamik Saha, Prabal Basu, Chidhambaranathan Rajamanikkam, Aatreyi Bal, Koushik Chakraborty, Sanghamitra Roy
2017	J	`jnl`	Security Measures Against a Rogue Network-on-Chip. J. Hardw. Syst. Secur. Rajesh Jayashankara Shridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2017	J	`jnl`	Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit. J. Low Power Electron. Asmita Pal, Aatreyi Bal, Koushik Chakraborty, Sanghamitra Roy
2016	A	`conf`	BoostNoC: power efficient network-on-chip architecture for near threshold computing. ICCAD Chidhambaranathan Rajamanikkam, Rajesh J. S., Koushik Chakraborty, Sanghamitra Roy
2016	A*	`conf`	Catching the flu: emerging threats from a third party power management unit. DAC Rajesh Jayashankara Shridevi, Chidhambaranathan Rajamanikkam, Koushik Chakraborty, Sanghamitra Roy
2016	A	`conf`	PRADA: Combating voltage noise in the NoC power supply through flow-control and routing algorithms. DATE Prabal Basu, Rajesh Jayashankara Shridevi, Koushik Chakraborty, Sanghamitra Roy
2016	A*	`conf`	SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost. DAC Prabal Basu, Hu Chen, Shamik Saha, Koushik Chakraborty, Sanghamitra Roy
2016	A*	`conf`	Synergistic timing speculation for multi-threaded programs. DAC Atif Yasin, Jeff Jun Zhang, Hu Chen, Siddharth Garg, Sanghamitra Roy, Koushik Chakraborty
2015	J	`jnl`	DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors. ACM Trans. Design Autom. Electr. Syst. Hu Chen, Sanghamitra Roy, Koushik Chakraborty
2015	A*	`conf`	Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks. DAC Hu Chen, Dieudonne Manzi, Sanghamitra Roy, Koushik Chakraborty
2015	J	`jnl`	Resilient Cache Design for Mobile Processors in the Near-Threshold Regime. J. Low Power Electron. Dieudonne Manzi Mugisha, Hu Chen, Sanghamitra Roy, Koushik Chakraborty
2015	—	`conf`	Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip. NOCS Rajesh J. S., Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2015	A	`conf`	Tackling voltage emergencies in NoC through timing error resilience. ISLPED Rajesh Jayashankara Shridevi, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2015	J	`jnl`	Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm. IEEE Trans. Very Large Scale Integr. Syst. Dean Michael Ancajas, Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
2014	A	`conf`	DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors. DATE Hu Chen, Sanghamitra Roy, Koushik Chakraborty
2014	J	`jnl`	Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight. IEEE Trans. Very Large Scale Integr. Syst. Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty
2014	—	`conf`	Exploiting static and dynamic locality of timing errors in robust L1 cache design. ISQED Hu Chen, Sanghamitra Roy, Koushik Chakraborty
2014	J	`jnl`	Exploring High-Throughput Computing Paradigm for Global Routing. IEEE Trans. Very Large Scale Integr. Syst. Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2014	A*	`conf`	Fort-NoCs: Mitigating the Threat of a Compromised NoC. DAC Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2014	Misc	`conf`	Tackling QoS-induced aging in exascale systems through agile path selection. CODES+ISSS Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy, Jason M. Allred
2013	C	`conf`	A global router on GPU architecture. ICCD Yiding Han, Koushik Chakraborty, Sanghamitra Roy
2013	J	`jnl`	Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. Koushik Chakraborty, Sanghamitra Roy
2013	A*	`conf`	DMR3D: dynamic memory relocation in 3D multicore systems. DAC Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2013	A*	`conf`	Efficiently tolerating timing violations in pipelined microprocessors. DAC Koushik Chakraborty, Brennan Cozzens, Sanghamitra Roy, Dean Michael Ancajas
2013	A*	`conf`	HCI-tolerant NoC router microarchitecture. DAC Dean Michael Ancajas, James McCabe Nickerson, Koushik Chakraborty, Sanghamitra Roy
2013	C	`conf`	Long term sustainability of differentially reliable systems in the dark silicon era. ICCD Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty
2013	A	`conf`	Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach. DATE Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2013	J	`jnl`	Using Adaptive Body Biasing for Robust Process Variation Aware DRAM Design. J. Low Power Electron. Satyajit Desai, Sanghamitra Roy
2012	A	`conf`	An MILP-based aging-aware routing algorithm for NoCs. DATE Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
2012	J	`jnl`	Analysis of intermittent timing fault vulnerability. Microelectron. Reliab. Saurabh Kothawade, Koushik Chakraborty, Sanghamitra Roy, Yiding Han
2012	C	`conf`	DOC: Fast and accurate congestion analysis for global routing. ICCD Yiding Han, Koushik Chakraborty, Sanghamitra Roy
2012	A	`conf`	Designing for dark silicon: a methodological perspective on energy efficient systems. ISLPED Jason M. Allred, Sanghamitra Roy, Koushik Chakraborty
2012	C	`conf`	Mitigating NBTI in the physical register file through stress prediction. ICCD Saurabh Kothawade, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2012	—	`conf`	Power-Performance Yield optimization for MPSoCs using MILP. ISQED Kshitij Bhardwaj, Sanghamitra Roy, Koushik Chakraborty
2012	A*	`conf`	Predicting timing violations through instruction-level path sensitization analysis. DAC Sanghamitra Roy, Koushik Chakraborty
2012	—	`conf`	Process variation aware DRAM design using block based adaptive body biasing algorithm. ISQED Satyajit Desai, Sanghamitra Roy, Koushik Chakraborty
2012	J	`jnl`	Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs. IEEE Trans. Very Large Scale Integr. Syst. Koushik Chakraborty, Sanghamitra Roy
2012	A*	`conf`	Towards graceful aging degradation in NoCs through an adaptive routing algorithm. DAC Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy
2011	Misc	`conf`	A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization. VLSI Design Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala
2011	—	`conf`	Analysis and mitigation of NBTI aging in register file: An end-to-end approach. ISQED Saurabh Kothawade, Koushik Chakraborty, Sanghamitra Roy
2011	J	`jnl`	Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm. ACM Trans. Design Autom. Electr. Syst. Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala
2011	J	`jnl`	Exploiting dynamic micro-architecture usage in gate sizing. Microprocess. Microsystems Sanghamitra Roy, Koushik Chakraborty
2011	A	`conf`	Exploring high throughput computing paradigm for global routing. ICCAD Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy
2011	—	`conf`	Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors. ISQED Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty
2011	J	`jnl`	Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework. J. Low Power Electron. Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty
2011	—	`conf`	Optimizing simulated annealing on GPU: A case study with IC floorplanning. ISQED Yiding Han, Sanghamitra Roy, Koushik Chakraborty
2011	A	`conf`	Topologically homogeneous power-performance heterogeneous multicore systems. DATE Koushik Chakraborty, Sanghamitra Roy
2010	J	`jnl`	A Novel Threshold Voltage Assignment for 3D Multicore Designs. J. Low Power Electron. Koushik Chakraborty, Sanghamitra Roy
2010	—	`conf`	A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures. ISQED Sanghamitra Roy, Koushik Chakraborty
2010	C	`conf`	Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization. ICCD Sanghamitra Roy, Koushik Chakraborty
2010	Misc	`conf`	Rethinking Threshold Voltage Assignment in 3D Multicore Designs. VLSI Design Koushik Chakraborty, Sanghamitra Roy
2008	—	`conf`	An optimal algorithm for sizing sequential circuits for industrial library based designs. ASP-DAC Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng
2008	—	`ch.`	Wire Sizing. Handbook of Algorithms for Physical Design Automation Sanghamitra Roy, Charlie Chung-Ping Chen
2007	J	`jnl`	Numerically Convex Forms and Their Application in Gate Sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu
2007	—	`conf`	SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. ASP-DAC Sanghamitra Roy, Charlie Chung-Ping Chen
2006	—	`conf`	ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. ISQED Sanghamitra Roy, Charlie Chung-Ping Chen
2005	J	`jnl`	An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design. IEEE Trans. Computers Sanghamitra Roy, Prith Banerjee
2005	A	`conf`	ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. ICCAD Sanghamitra Roy, Weijen Chen
2004	A*	`conf`	An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. DAC Sanghamitra Roy, Prithviraj Banerjee
2004	A	`conf`	An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. FPGA Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee
2003	J	`jnl`	Hierarchical representation of digitized curves through dominant point detection. Pattern Recognit. Lett. Biswajit Sarkar, Sanghamitra Roy, Debranjan Sarkar