Sang H. Dhong - RankMe

34 papers A* 1A 2C 3Misc 1Journal 19Unranked 8

Year	Rank	Type	Title / Venue / Authors
2015	—	`conf`	Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang
2014	—	`conf`	A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. CICC Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang
2014	—	`conf`	A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang
2013	—	`conf`	A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm CICC Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong
2013	—	`conf`	Prospective for nanowire transistors. CICC Jean-Pierre Colinge, Sang H. Dhong
2008	A	`conf`	Challenges at 45nm and beyond. ICCAD Dan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong
2007	—	`conf`	Cell Broadband Engine Processor Design Methodology. CICC Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny
2007	—	`conf`	Implementation of the 65nm Cell Broadband Engine. CICC Mack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino
2007	J	`jnl`	Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata
2006	—	`conf`	A cycle accurate power estimation tool. ASP-DAC Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong
2006	J	`jnl`	A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor. IEEE J. Solid State Circuits Hwa-Joon Oh, Silvia M. Müller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong
2006	J	`jnl`	Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. IEEE J. Solid State Circuits James D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen
2006	J	`jnl`	The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata
2005	J	`jnl`	Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. IEEE Micro Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara
2005	J	`jnl`	Power-Conscious Design of the Cell Processor's Synergistic Processor Element. IEEE Micro Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman
2005	C	`conf`	The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. IEEE Symposium on Computer Arithmetic Silvia M. Müller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong
2005	A	`conf`	The circuit design of the synergistic processor element of a CELL processor. ICCAD Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman
2000	A*	`conf`	"Timing closure by design, " a high frequency microprocessor design methodology. DAC Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia
2000	J	`jnl`	1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. IEEE J. Solid State Circuits Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki
2000	J	`jnl`	Custom circuit design as a driver of microprocessor performance. IBM J. Res. Dev. David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
1999	J	`jnl`	A 1-GHz logic circuit family with sense amplifiers. IEEE J. Solid State Circuits Osamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong
1998	J	`jnl`	A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric
1998	C	`conf`	A 690 ps read-access latency register file for a GHz integer microprocessor. ICCD Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki
1998	C	`conf`	Design methodology for a 1.0 GHz microprocessor. ICCD Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo
1998	J	`jnl`	Designing for a gigahertz [guTS integer processor]. IEEE Micro H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi
1998	Misc	`conf`	High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor. VTS David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz
1995	J	`jnl`	A 64Kb - 32 DRAM for graphics applications. IBM J. Res. Dev. Toshio Sunaga, Koji Hosokawa, Sang H. Dhong, Koji Kitamura
1995	J	`jnl`	A low-noise TTL-compatible CMOS off-chip driver circuit. IBM J. Res. Dev. Sang H. Dhong, Masahiro Tanaka, Steven W. Tomashot, Toshiaki Kirihata
1995	J	`jnl`	A variable precharge voltage sensing. IEEE J. Solid State Circuits Toshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira
1992	J	`jnl`	A 14-ns 14-Mb CMOS DRAM with 300-mW active power. IEEE J. Solid State Circuits Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa
1992	J	`jnl`	A large V IEEE J. Solid State Circuits Robert L. Franch, Sang H. Dhong, Roy E. Scheuerlein
1992	J	`jnl`	A pulsed sensing scheme with a limited bit-line swing. IEEE J. Solid State Circuits Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong
1989	J	`jnl`	A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. IEEE J. Solid State Circuits Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano
1988	J	`jnl`	High-speed sensing scheme for CMOS DRAMs. IEEE J. Solid State Circuits Sang H. Dhong, Nicky Chau-Chun Lu, Wei Hwang, Stephen A. Parke