Sang-Hyeok Chu

12 papers Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2020 — conf
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier.
ISSCC
Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee, Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin
2020 J jnl
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Jeongho Hwang, Sang-Hyeok Chu, Gyu-Seob Jeong, Yeojoon Youn, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
2018 — conf
A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS.
BCICTS
Jeongho Hwang, Gyu-Seob Jeong, Sang-Hyeok Chu, Wooseok Kim, Taeik Kim, Deog-Kyoon Jeong
2017 J jnl
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel.
IEEE Trans. Circuits Syst. II Express Briefs
Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong
2016 J jnl
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G
IEEE J. Solid State Circuits
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2015 — conf
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
A-SSCC
Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong
2015 J jnl
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process.
IEEE J. Solid State Circuits
Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2015 — conf
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
ESSCIRC
Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong
2015 J jnl
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.
IEEE Trans. Circuits Syst. II Express Briefs
Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2015 — conf
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation.
VLSIC
Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong
2014 — conf
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.
A-SSCC
Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong
2014 J jnl
A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
Taeho Kim, Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Jiheon Park, Deog-Kyoon Jeong