Sandro Bartolini

60 papers A 4C 8Misc 1Journal 32Unranked 8

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Low-Cost Multi-Objective Cache Prefetcher for Complex and Irregular Memory Access Patterns. IEEE Access Elham Cheshmikhani, Hamed Farbeh, Sandro Bartolini
2025	J	`jnl`	Application of LSTM and GRU neural networks to improve peristaltic pump dosing accuracy. Intell. Syst. Appl. Davide Privitera, Stefano Bellissima, Sandro Bartolini
2025	J	`jnl`	Ensemble Methods for Peristaltic Pump Accuracy Enhancement. IEEE Access Davide Privitera, Alessandro Mecocci, Sandro Bartolini
2025	J	`jnl`	High-Performance Multi-Object Tracking for Autonomous Driving in Urban Scenarios With Heterogeneous Embedded Boards. IEEE Access Alessio Medaglini, Biagio Peccerillo, Sandro Bartolini
2024	C	`conf`	DeVAS: Decoupled Virtual Address Spaces. SBAC-PAD Mirco Mannino, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini
2024	—	`conf`	Integration of RISC-V Page Table Walk in gem5 SE Mode. RAPIDO@HiPEAC Mirco Mannino, Yinting Huang, Biagio Peccerillo, Alessio Medaglini, Sandro Bartolini
2023	J	`jnl`	Adaptive Dosing Control System Through ARIMA Model for Peristaltic Pumps. IEEE Access Davide Privitera, Stefano Bellissima, Sandro Bartolini
2023	J	`jnl`	Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors. IEEE Access Mirco Mannino, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini
2023	—	`conf`	Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support. CF Mirco Mannino, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini
2023	J	`jnl`	IXIAM: ISA EXtension for Integrated Accelerator Management. IEEE Access Biagio Peccerillo, Elham Cheshmikhani, Mirco Mannino, Andrea Mondelli, Sandro Bartolini
2023	—	`conf`	Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles. MECO Alessio Medaglini, Sandro Bartolini, Gianluca Mandò, Eduardo Quiñones, Sara Royuela
2022	J	`jnl`	A General Framework for Accelerator Management Based on ISA Extension. IEEE Access Elham Cheshmikhani, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini
2022	J	`jnl`	A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives. J. Syst. Archit. Biagio Peccerillo, Mirco Mannino, Andrea Mondelli, Sandro Bartolini
2022	J	`jnl`	Applying Intel's oneAPI to a machine learning case study. Concurr. Comput. Pract. Exp. Pablo Antonio Martínez, Biagio Peccerillo, Sandro Bartolini, José M. García, Gregorio Bernabé
2022	J	`jnl`	Flexible task-DAG management in PHAST library: Data-parallel tasks and orchestration support for heterogeneous systems. Concurr. Comput. Pract. Exp. Biagio Peccerillo, Sandro Bartolini
2022	J	`jnl`	Performance portability in a real world application: PHAST applied to Caffe. Int. J. High Perform. Comput. Appl. Pablo Antonio Martínez, Biagio Peccerillo, Sandro Bartolini, José M. García, Gregorio Bernabé
2020	J	`jnl`	Using PHAST to port Caffe library: First experiences and lessons learned. CoRR Eduardo José Gómez-Hernández, Pablo Antonio Martínez, Biagio Peccerillo, Sandro Bartolini, José Manuel García Carrasco, Gregorio Bernabé
2019	J	`jnl`	PHAST - A Portable High-Level Modern C++ Programming Library for GPUs and Multi-Cores. IEEE Trans. Parallel Distributed Syst. Biagio Peccerillo, Sandro Bartolini
2019	J	`jnl`	Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs. J. Cryptogr. Eng. Biagio Peccerillo, Sandro Bartolini, Çetin Kaya Koç
2019	—	`conf`	Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous Architectures. PMAM@PPoPP Biagio Peccerillo, Sandro Bartolini
2018	J	`jnl`	Augmented Virtuality for Coastal Management: A Holistic Use of In Situ and Remote Sensing for Large Scale Definition of Coastal Dynamics. ISPRS Int. J. Geo Inf. Sandro Bartolini, Alessandro Mecocci, Alessandro Pozzebon, Claudia Zoppetti, Duccio Bertoni, Giovanni Sarti, Andrea Caiti, Riccardo Costanzi, Filippo Catani, Andrea Ciampalini, Sandro Moretti
2018	J	`jnl`	Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems. Future Gener. Comput. Syst. Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
2018	—	`ch.`	Parallel Programming in Cyber-Physical Systems. Cyber-Physical Systems Security Sandro Bartolini, Biagio Peccerillo
2018	J	`jnl`	Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs. ACM J. Emerg. Technol. Comput. Syst. Paolo Grani, Sandro Bartolini
2017	—	`conf`	PHAST Library - Enabling Single-Source and High Performance Code for GPUs and Multi-cores. HPCS Biagio Peccerillo, Sandro Bartolini
2016	—	`ed.`	Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016 AISTECS@HiPEAC Sören Sonntag, Sandro Bartolini, Giorgos Dimitrakopoulos, José M. García
2015	Misc	`conf`	Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects. ICNC Paolo Grani, Robert Hendry, Sandro Bartolini, Keren Bergman
2014	A	`conf`	Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline. DATE Luca Ramini, Alberto Ghiribaldi, Paolo Grani, Sandro Bartolini, Hervé Tatenguem Fankem, Davide Bertozzi
2014	J	`jnl`	Design Options for Optical Ring Interconnect in Future Client Devices. ACM J. Emerg. Technol. Comput. Syst. Paolo Grani, Sandro Bartolini
2014	J	`jnl`	Exploiting silicon photonics for energy-efficient heterogeneous parallel architectures. Concurr. Comput. Pract. Exp. Sandro Bartolini, José M. García
2014	J	`jnl`	Managing resources dynamically in hybrid photonic-electronic networks-on-chip. Concurr. Comput. Pract. Exp. Antonio García-Guirado, Ricardo Fernández-Pascual, José M. García, Sandro Bartolini
2014	—	`conf`	Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs. HPCC/CSS/ICESS Paolo Grani, Sandro Bartolini
2014	C	`conf`	Solving Graph Partitioning Problems Arising in Tagless Cache Management. ISCO Sandro Bartolini, Iacopo Casini, Paolo Detti
2014	—	`conf`	Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems. NOCS Luca Ramini, Hervé Tatenguem Fankem, Alberto Ghiribaldi, Paolo Grani, Marta Ortín-Obón, Anja Boos, Sandro Bartolini
2013	—	`conf`	Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs. MES Sandro Bartolini, Paolo Grani
2013	A	`conf`	Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis. DATE Luca Ramini, Paolo Grani, Sandro Bartolini, Davide Bertozzi
2013	C	`conf`	Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors. DSD Sandro Bartolini, Luca Lusnig, Enrico Martinelli
2012	C	`conf`	A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs. DSD Sandro Bartolini, Paolo Grani
2011	J	`jnl`	Eighth MEDEA Workshop. Trans. High Perform. Embed. Archit. Compil. Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
2011	A	`conf`	Link-time optimization for power efficiency in a tagless instruction cache. CGO Timothy M. Jones, Sandro Bartolini, Jonas Maebe, Dominique Chanet
2010	C	`conf`	Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs. SBAC-PAD Sandro Bartolini, Pierfrancesco Foglia, Marco Solinas, Cosimo Antonio Prete
2009	—	`ch.`	Instruction Set Extensions for Cryptographic Applications. Cryptographic Engineering Sandro Bartolini, Roberto Giorgi, Enrico Martinelli
2009	—	`ed.`	Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009 MEDEA@PACT Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2008	J	`jnl`	Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2 IEEE Trans. Computers Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
2008	A	`conf`	Instruction Cache Energy Saving Through Compiler Way-Placement. DATE Timothy M. Jones, Sandro Bartolini, Bruno De Bus, John Cavazos, Michael F. P. O'Boyle
2008	—	`ed.`	Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008 MEDEA@PACT Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi
2007	C	`conf`	Inclusion of a Montgomery Multiplier Unit into an Embedded Processor's Datapath to Speed-up Elliptic Curve Cryptography. IAS Sandro Bartolini, Cinzia Castagnini, Enrico Martinelli
2007	J	`jnl`	MEmory performance: DEaling with applications, systems and architecture. SIGARCH Comput. Archit. News Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
2007	—	`ed.`	Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007 MEDEA@PACT Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi
2006	J	`jnl`	Embedded processors and systems: Architectural issues and solutions for emerging applications. J. Embed. Comput. Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
2006	J	`jnl`	Issues in Embedded Single-Chip Multicore Architectures. J. Embed. Comput. Sandro Bartolini, Roberto Giorgi
2006	J	`jnl`	Memory performance: dealing with applications, systems and architecture. SIGARCH Comput. Archit. News Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2005	J	`jnl`	Guests editor's introduction. SIGARCH Comput. Archit. News Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
2005	J	`jnl`	Optimizing instruction cache performance of embedded systems. ACM Trans. Embed. Comput. Syst. Sandro Bartolini, Cosimo Antonio Prete
2004	C	`conf`	A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. SBAC-PAD Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
2004	J	`jnl`	A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications. SIGARCH Comput. Archit. News Sandro Bartolini, Cosimo Antonio Prete
2004	—	`ed.`	Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004 MEDEA@PACT Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
2002	J	`jnl`	A cache-aware program transformation technique suitable for embedded systems. Inf. Softw. Technol. Sandro Bartolini, Cosimo Antonio Prete
2001	C	`conf`	An Object Level Transformation Technique to Improve the Performance of Embedded Applications. SCAM Sandro Bartolini, Cosimo Antonio Prete
2001	J	`jnl`	Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. SIGARCH Comput. Archit. News Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, Mateo Valero