| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2017 | — | conf |
ICRC
|
| 2015 | J | jnl |
Proc. IEEE
|
| 2014 | J | jnl |
ACM J. Emerg. Technol. Comput. Syst.
|
| 2012 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2012 | — | conf |
ESSDERC
|
| 2011 | J | jnl |
IEICE Trans. Electron.
|
| 2011 | — | conf |
NANOARCH
|
| 2007 | Misc | conf |
VLSI Design
|
| 2006 | J | jnl |
Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space.
IEEE Trans. Circuits Syst. II Express Briefs
|
| 2005 | J | jnl |
Microelectron. J.
|
| 2005 | J | jnl |
IEEE Des. Test Comput.
|
| 2005 | — | conf |
ISCAS (3)
|
| 2004 | — | conf |
ISCAS (1)
|
| 2004 | — | conf |
SLIP
|
| 2004 | — | conf |
DFT
|