Sandip Kundu - RankMe

272 papers A* 4A 38B 7C 30Misc 18Journal 76Unranked 98

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	Thermal Runaway Analysis of Analog PIM Accelerators. VLSID Huatao Wu, Sandip Kundu
2025	Misc	`conf`	A Study on Efficiency Improvements of DNN Accelerators via Denormalized Arithmetic Elimination. VLSID Alexander Kharitonov, Sandip Kundu
2025	—	`conf`	Managing Computation Offloading from Edge Devices to a Reconfigurable Edge Cloud. ASAP Zhehang Zhang, Bharadwaj Madabhushi, Sandip Kundu, Russell Tessier
2024	—	`conf`	A Novel Self-Repair Mechanism for Tiled Matrix Multiplication Unit. DFT Chandra Sekhar Mummidi, Sandeep Bal, Sandip Kundu
2024	J	`jnl`	Extracting DNN Architectures via Runtime Profiling on Mobile GPUs. IEEE J. Emerg. Sel. Topics Circuits Syst. Dong Hyub Kim, Jonah O'Brien Weiss, Sandip Kundu
2024	J	`jnl`	Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators. ACM Trans. Archit. Code Optim. Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan, Sandip Kundu
2024	A	`conf`	Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes. DATE Bharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb
2024	J	`jnl`	Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes. CoRR Bharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb
2024	—	`conf`	Resurrection Attack: Defeating Xilinx MPU's Memory Protection. HOST Bharadwaj Madabhushi, Chandra Sekhar Mummidi, Sandip Kundu, Daniel E. Holcomb
2024	J	`jnl`	Resurrection Attack: Defeating Xilinx MPU's Memory Protection. CoRR Bharadwaj Madabhushi, Chandra Sekhar Mummidi, Sandip Kundu, Daniel E. Holcomb
2024	—	`conf`	Security Risks Due to Data Persistence in Cloud FPGA Platforms. MWSCAS Zhehang Zhang, Bharadwaj Madabhushi, Sandip Kundu, Russell Tessier
2024	J	`jnl`	Security Risks Due to Data Persistence in Cloud FPGA Platforms. CoRR Zhehang Zhang, Bharadwaj Madabhushi, Sandip Kundu, Russell Tessier
2023	—	`conf`	A Neural Network-Based Approach to Dynamic Core Morphing for AMPs. iSES Chandra Sekhar Mummidi, Sandip Kundu
2023	A	`conf`	A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication. DATE Sandeep Bal, Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan, Sandip Kundu
2023	J	`jnl`	ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures. ACM Trans. Archit. Code Optim. Chandra Sekhar Mummidi, Sandip Kundu
2023	J	`jnl`	EZClone: Improving DNN Model Extraction Attack via Shape Distillation from GPU Execution Profiles. CoRR Jonah O'Brien Weiss, Tiago A. O. Alves, Sandip Kundu
2023	C	`conf`	NUMAlloc: A Faster NUMA Memory Allocator. ISMM Hanmei Yang, Xin Zhao, Jin Zhou, Wei Wang, Sandip Kundu, Bo Wu, Hui Guan, Tongping Liu
2022	C	`conf`	A Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture. ICCD Chandra Sekhar Mummidi, Sandeep Bal, Brunno F. Goldstein, Sudarshan Srinivasan, Sandip Kundu
2022	C	`conf`	A Software Approach Towards Defeating Power Management Side Channel Leakage. IOLTS Md. Nazmul Islam, Sandip Kundu
2022	—	`conf`	Analysis of Fake News Classification for Insight into the Roles of Different Data Types. ICSC Victor da Cruz Ferreira, Sandip Kundu, Felipe M. G. França
2022	—	`conf`	Hardening DNNs against Transfer Attacks during Network Compression using Greedy Adversarial Pruning. AICAS Jonah O'Brien Weiss, Tiago A. O. Alves, Sandip Kundu
2022	J	`jnl`	Hardening DNNs against Transfer Attacks during Network Compression using Greedy Adversarial Pruning. CoRR Jonah O'Brien Weiss, Tiago A. O. Alves, Sandip Kundu
2022	J	`jnl`	Realizing Robust, Lightweight Strong PUFs for Securing Smart Grids. IEEE Trans. Consumer Electron. Vinay C. Patil, Sandip Kundu
2022	—	`conf`	Reinforcement Learning based Multi-Attribute Slice Admission Control for Next-Generation Networks in a Dynamic Pricing Environment. VTC Spring Victor da Cruz Ferreira, Haitham H. Esmat, Beatriz Lorenzo, Sandip Kundu, Felipe M. G. França
2022	J	`jnl`	Remote Device Management via Smart Contracts. IEEE Trans. Consumer Electron. Md. Nazmul Islam, Sandip Kundu
2021	—	`conf`	A Lightweight Error-Resiliency Mechanism for Deep Neural Networks. ISQED Brunno F. Goldstein, Victor da Cruz Ferreira, Sudarshan Srinivasan, Dipankar Das, Alexandre Solon Nery, Sandip Kundu, Felipe M. G. França
2021	J	`jnl`	Concurrency Analysis in Dynamic Dataflow Graphs. IEEE Trans. Emerg. Top. Comput. Tiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu, Felipe M. G. França
2021	A	`conf`	MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs. DSN Jonathan Ponader, Kyle Thomas, Sandip Kundu, Yan Solihin
2021	J	`jnl`	Preventing DNN Model IP Theft via Hardware Obfuscation. IEEE J. Emerg. Sel. Topics Circuits Syst. Brunno F. Goldstein, Vinay C. Patil, Victor da Cruz Ferreira, Alexandre Solon Nery, Felipe M. G. França, Sandip Kundu
2020	—	`conf`	Building a portable deeply-nested implicit information flow tracking. CF Leandro Santiago de Araújo, Leandro A. J. Marzulo, Tiago A. O. Alves, Felipe M. G. França, Israel Koren, Sandip Kundu
2020	J	`jnl`	Deep-Lock: Secure Authorization for Deep Neural Networks. CoRR Manaar Alam, Sayandeep Saha, Debdeep Mukhopadhyay, Sandip Kundu
2020	—	`ch.`	IoT Security, Privacy and Trust in Home-Sharing Economy via Blockchain. Blockchain Cybersecurity, Trust and Privacy Md. Nazmul Islam, Sandip Kundu
2020	J	`jnl`	MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs. CoRR Jonathan Ponader, Sandip Kundu, Yan Solihin
2020	—	`conf`	On Leveraging Multi-threshold FinFETs for Design Obfuscation. ISVLSI Vinay C. Patil, Sandip Kundu
2020	C	`conf`	Reduced Fault Coverage as a Target for Design Scaffolding Security. IOLTS Irith Pomeranz, Sandip Kundu
2020	—	`conf`	Reliability Evaluation of Compressed Deep Learning Models. LASCAS Brunno F. Goldstein, Sudarshan Srinivasan, Dipankar Das, Kunal Banerjee, Leandro Santiago de Araújo, Victor da Cruz Ferreira, Alexandre Solon Nery, Sandip Kundu, Felipe M. G. França
2020	B	`conf`	Towards Adversarial Attack Resistant Deep Neural Networks. ESANN Tiago A. O. Alves, Sandip Kundu
2020	J	`jnl`	Weightless Neural Networks as Memory Segmented Bloom Filters. Neurocomputing Leandro Santiago, Letícia Dias Verona, Fábio Medeiros Rangel, Fabrício Firmino de Faria, Daniel S. Menasché, Wouter Caarls, Maurício Breternitz Jr., Sandip Kundu, Priscila M. V. Lima, Felipe M. G. França
2019	J	`jnl`	Design of Robust, High-Entropy Strong PUFs via Weightless Neural Network. J. Hardw. Syst. Secur. Leandro Santiago de Araújo, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu
2019	—	`conf`	Efficient Testing of Physically Unclonable Functions for Uniqueness. ATS Leandro Santiago de Araújo, Vinay C. Patil, Leandro Augusto Justen Marzulo, Felipe Maia Galvão França, Sandip Kundu
2019	J	`jnl`	Enabling IC Traceability via Blockchain Pegged to Embedded PUF. ACM Trans. Design Autom. Electr. Syst. Md. Nazmul Islam, Sandip Kundu
2019	—	`conf`	Hardware-Accelerated Similarity Search with Multi-Index Hashing. DASC/PiCom/DataCom/CyberSciTech Leandro Santiago de Araújo, Victor da Cruz Ferreira, Brunno Figueiroa Goldstein, Alexandre Solon Nery, Leandro Augusto Justen Marzulo, Sandip Kundu, Felipe Maia Galvão França
2019	—	`conf`	MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning Systems. ACM Great Lakes Symposium on VLSI Tiago A. O. Alves, Felipe M. G. França, Sandip Kundu
2019	—	`conf`	MPP Keynote 1. IPDPS Workshops Sandip Kundu
2019	B	`conf`	Memory Efficient Weightless Neural Network using Bloom Filter. ESANN Leandro Santiago de Araújo, Letícia Dias Verona, Fábio Medeiros Rangel, Fabrício Firmino de Faria, Daniel Sadoc Menasché, Wouter Caarls, Maurício Breternitz, Sandip Kundu, Priscila Machado Vieira Lima, Felipe Maia Galvão França
2019	—	`conf`	Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De
2019	J	`jnl`	Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques. CoRR Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu
2019	—	`conf`	Remote Configuration of Integrated Circuit Features and Firmware Management via Smart Contract. Blockchain Md. Nazmul Islam, Sandip Kundu
2018	—	`conf`	Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance. CF Anderson Luiz Sartor, Arthur Francisco Lorenzon, Sandip Kundu, Israel Koren, Antonio C. S. Beck
2018	—	`conf`	Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs. AsianHOST Horacio L. França, Charles B. Prado, Vinay C. Patil, Sandip Kundu
2018	J	`jnl`	On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging. IEEE Trans. Circuits Syst. I Regul. Pap. Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu
2018	—	`conf`	On IC traceability via blockchain. VLSI-DAT Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu
2018	—	`conf`	PMU-Trojan: On exploiting power management side channel for information leakage. ASP-DAC Md. Nazmul Islam, Sandip Kundu
2018	—	`conf`	Poster Abstract: Preserving IoT Privacy in Sharing Economy Via Smart Contract. IoTDI Md. Nazmul Islam, Sandip Kundu
2018	—	`conf`	Poster Abstract: Privacy in Blockchain-Enabled IoT Devices. IoTDI Arman Pouraghily, Md. Nazmul Islam, Sandip Kundu, Tilman Wolf
2017	C	`conf`	A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF. ISCAS Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu
2017	—	`conf`	A resilient scheduler for dataflow execution. DFT Tiago A. O. Alves, Sandip Kundu, Leandro A. J. Marzulo, Felipe M. G. França
2017	Misc	`conf`	An analytical model for predicting the residual life of an IC and design of residual-life meter. VTS Md. Nazmul Islam, Sandip Kundu
2017	—	`conf`	Determining proximal geolocation of IoT edge devices via covert channel. ISQED Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu
2017	J	`jnl`	Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions. IEEE Trans. Very Large Scale Integr. Syst. Anirban Sengupta, Sandip Kundu
2017	—	`conf`	Improving reliability of weak PUFs via circuit techniques to enhance mismatch. HOST Vinay C. Patil, Arunkumar Vijayakumar, Daniel E. Holcomb, Sandip Kundu
2017	—	`conf`	Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment. NATW Pavithra Ramesh, Vinay C. Patil, Sandip Kundu
2017	J	`jnl`	Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques. IEEE Trans. Inf. Forensics Secur. Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu
2017	—	`conf`	Realizing strong PUF from weak PUF via neural computing. DFT Leandro Santiago, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu
2016	J	`jnl`	Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, Sandip Kundu
2016	Misc	`conf`	An Efficient Method for Clock Skew Scheduling to Reduce Peak Current. VLSID Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu
2016	Misc	`conf`	Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors. VLSID Sudarshan Srinivasan, Nithesh Kurella, Israel Koren, Sandip Kundu
2016	Misc	`conf`	Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores. VLSID Sandip Kundu, Omer Khan
2016	J	`jnl`	Exploring Heterogeneity within a Core for Improved Power Efficiency. IEEE Trans. Parallel Distributed Syst. Sudarshan Srinivasan, Nithesh Kurella, Israel Koren, Sandip Kundu
2016	J	`jnl`	Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. IEEE Trans. Computers Cristiana Bolchini, Sandip Kundu, Salvatore Pontarelli
2016	C	`conf`	Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification. ICCD Sudarshan Srinivasan, Israel Koren, Sandip Kundu
2016	—	`conf`	Machine learning resistant strong PUF: Possible or a pipe dream? HOST Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, Sandip Kundu
2016	—	`conf`	Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing. ATS Sandip Kundu
2016	J	`jnl`	Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vikram B. Suresh, Sandip Kundu
2016	—	`conf`	Modeling Residual Life of an IC Considering Multiple Aging Mechanisms. NATW Md. Nazmul Islam, Sandip Kundu
2016	—	`conf`	Modeling Residual Lifetime of an IC Considering Spatial and Inter-Temporal Temperature Variations. ATS Md. Nazmul Islam, Sandip Kundu
2016	—	`conf`	On meta-obfuscation of physical layouts to conceal design characteristics. DFT Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu
2016	—	`conf`	On testing physically unclonable functions for uniqueness. ISQED Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu
2016	—	`conf`	Preventing integrated circuit piracy via custom encoding of hardware instruction set. ISQED Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu
2015	J	`jnl`	A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors. ACM Trans. Embed. Comput. Syst. Abhisek Pan, Rance Rodrigues, Sandip Kundu
2015	A	`conf`	A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics. DATE Arunkumar Vijayakumar, Sandip Kundu
2015	J	`jnl`	Does the Sharing of Execution Units Improve Performance/Power of Multicores? ACM Trans. Embed. Comput. Syst. Rance Rodrigues, Israel Koren, Sandip Kundu
2015	J	`jnl`	Guest Editorial: Special Section on Circuit and System Design Methodologies for Emerging Technologies. IEEE Trans. Emerg. Top. Comput. Saraju P. Mohanty, Sandip Kundu
2015	C	`conf`	Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core. ICCD Sudarshan Srinivasan, Israel Koren, Sandip Kundu
2014	—	`conf`	A Chaotic Ring oscillator based Random Number Generator. HOST Siva Nishok Dhanuskodi, Arunkumar Vijayakumar, Sandip Kundu
2014	J	`jnl`	A low-power instruction replay mechanism for design of resilient microprocessors. ACM Trans. Embed. Comput. Syst. Rance Rodrigues, Arunachalam Annamalai, Sandip Kundu
2014	B	`conf`	A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency. PACT Sudarshan Srinivasan, Nithesh Kurella, Israel Koren, Rance Rodrigues, Sandip Kundu
2014	—	`conf`	Domino effect protection on dataflow error detection and recovery. DFT Tiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu, Felipe Maia Galvão França
2014	—	`conf`	Glitch Power Reduction via Clock Skew Scheduling. ISVLSI Arunkumar Vijayakumar, Sandip Kundu
2014	J	`jnl`	Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2014	—	`conf`	Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip. ISVLSI Bharath Phanibhushana, Sandip Kundu
2014	Misc	`conf`	On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions. VLSID Raghavan Kumar, Siva Nishok Dhanuskodi, Sandip Kundu
2014	—	`conf`	On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery. ISVLSI Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu
2014	—	`conf`	On pattern generation for maximizing IR drop. ISQED Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu
2014	C	`conf`	Online error detection and recovery in dataflow execution. IOLTS Tiago A. O. Alves, Sandip Kundu, Leandro A. J. Marzulo, Felipe Maia Galvão França
2014	Misc	`conf`	Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core. VLSID Rance Rodrigues, Israel Koren, Sandip Kundu
2014	J	`jnl`	Performance-driven dynamic thermal management of MPSoC based on task rescheduling. ACM Trans. Design Autom. Electr. Syst. Kunal P. Ganeshpure, Sandip Kundu
2014	—	`conf`	Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores. ISVLSI Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu
2013	J	`jnl`	A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2013	J	`jnl`	A Study on the Use of Performance Counters to Estimate Power in Microprocessors. IEEE Trans. Circuits Syst. II Express Briefs Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu
2013	—	`conf`	A low power architecture for online detection of execution errors in SMT processors. DFTS Rance Rodrigues, Sandip Kundu
2013	—	`conf`	A study on polymorphing superscalar processor dynamically to improve power efficiency. ISVLSI Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu
2013	—	`conf`	A system-level solution for managing spatial temperature gradients in thinned 3D ICs. ISQED Arunachalam Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, Sandip Kundu
2013	B	`conf`	An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs. PACT Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu
2013	J	`jnl`	Game theoretic approach for run-time task scheduling on an multi-processor system on chip. IET Circuits Devices Syst. Kunal P. Ganeshpure, Sandip Kundu
2013	J	`jnl`	Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits. IET Circuits Devices Syst. Sandip Kundu, Saraju P. Mohanty, Nagarajan Ranganathan
2013	Misc	`conf`	Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. VLSI Design Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu
2013	C	`conf`	Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array. ICCD Vikram B. Suresh, Sandip Kundu
2013	—	`conf`	On analyzing and mitigating SRAM BER due to random thermal noise. ISVLSI Vikram B. Suresh, Sandip Kundu
2013	C	`conf`	On dynamic polymorphing of a superscalar core for improving energy efficiency. ICCD Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu
2013	—	`conf`	On runtime task graph extraction in MPSoC. ISVLSI Kunal P. Ganeshpure, Sandip Kundu
2013	—	`conf`	Program phase duration prediction and its application to fine-grain power management. ISVLSI Sudarshan Srinivasan, Raghavan Kumar, Sandip Kundu
2012	—	`conf`	A DFT Methodology for Repairing Embedded Memories of Large MPSoCs. ISVLSI Kunal P. Ganeshpure, Sandip Kundu
2012	J	`jnl`	A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays. IEEE Trans. Computers Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu
2012	J	`jnl`	A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu
2012	—	`conf`	A mechanism to verify cache coherence transactions in multicore systems. DFT Rance Rodrigues, Israel Koren, Sandip Kundu
2012	—	`conf`	Critical area driven dummy fill insertion to improve manufacturing yield. ISQED Nishant Dhumane, Sandip Kundu
2012	—	`conf`	Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt. IPDPS Workshops Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu
2012	J	`jnl`	Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime. IET Circuits Devices Syst. Omer Khan, Sandip Kundu
2012	—	`conf`	Functional test pattern generation for maximizing temperature in 3D IC chip stack. ISQED Sudarshan Srinivasan, Sandip Kundu
2012	J	`jnl`	Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing. ACM Trans. Design Autom. Electr. Syst. Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu
2012	—	`conf`	On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors. ISVLSI Arunkumar Vijayakumar, Raghavan Kumar, Sandip Kundu
2012	—	`conf`	On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators. ISVLSI Raghavan Kumar, Vinay C. Patil, Sandip Kundu
2012	J	`jnl`	On Reliability Trojan Injection and Detection. J. Low Power Electron. Aswin Sreedhar, Sandip Kundu, Israel Koren
2012	J	`jnl`	On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs. J. Electron. Test. Michael Buttrick, Sandip Kundu
2012	—	`conf`	On lithography aware metal-fill insertion. ISQED Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu
2012	—	`conf`	Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes. ISVLSI Kunal P. Ganeshpure, Sandip Kundu
2012	C	`conf`	Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency. SBAC-PAD Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu
2012	J	`jnl`	Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays. IEEE Trans. Very Large Scale Integr. Syst. Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
2011	—	`conf`	An Architecture to Enable Life Cycle Testing in CMPs. DFT Rance Rodrigues, Israel Koren, Sandip Kundu
2011	B	`conf`	An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors. PACT Rance Rodrigues, Israel Koren, Sandip Kundu
2011	—	`conf`	An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors. Asian Test Symposium Rance Rodrigues, Sandip Kundu
2011	—	`conf`	Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain. ISVLSI Raghavan Kumar, Vinay C. Patil, Sandip Kundu
2011	—	`conf`	Efficient BDD-based Fault Simulation in Presence of Unknown Values. Asian Test Symposium Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich
2011	J	`jnl`	Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. IEEE Trans. Dependable Secur. Comput. Omer Khan, Sandip Kundu
2011	—	`conf`	Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability. ISVLSI Nishant Dhumane, Sudheendra K. Srivathsa, Sandip Kundu
2011	A	`conf`	Lithography aware critical area estimation and yield analysis. ITC Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu
2011	—	`conf`	Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloads. ISQED Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu
2011	J	`jnl`	Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. Trans. High Perform. Embed. Archit. Compil. Omer Khan, Sandip Kundu
2011	—	`conf`	Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs. ISVLSI Michael Buttrick, Sandip Kundu
2011	—	`conf`	Model based double patterning lithography (DPL) and simulated annealing (SA). ISQED Rance Rodrigues, Sandip Kundu
2011	A	`conf`	Modeling manufacturing process variation for design and test. DATE Sandip Kundu, Aswin Sreedhar
2011	—	`conf`	On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements. ISVLSI Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu
2011	A	`conf`	On design of test structures for lithographic process corner identification. DATE Aswin Sreedhar, Sandip Kundu
2011	—	`conf`	On discovery of "missing" physical design rules via diagnosis of soft-faults. ISQED Aswin Sreedhar, Sandip Kundu
2011	C	`conf`	On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units. IOLTS Rance Rodrigues, Sandip Kundu
2011	C	`conf`	On graceful degradation of microprocessors in presence of faults via resource banking. IOLTS Rance Rodrigues, Sandip Kundu
2011	—	`conf`	On improving reliability of delay based Physically Unclonable Functions under temperature variations. HOST Raghavan Kumar, Harikrishnan Kumarapillai Chandrikakutty, Sandip Kundu
2011	A	`conf`	On testing prebond dies with incomplete clock networks in a 3D IC using DLLs. DATE Michael Buttrick, Sandip Kundu
2011	B	`conf`	Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. PACT Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan
2011	A	`conf`	Physically unclonable functions for embeded security based on lithographic variation. DATE Aswin Sreedhar, Sandip Kundu
2011	—	`conf`	Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits. ACM Great Lakes Symposium on VLSI Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu
2011	C	`conf`	Task model for on-chip communication infrastructure design for multicore systems. ICCD Bharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu
2010	J	`jnl`	A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains. IEEE Trans. Circuits Syst. II Express Briefs Hyunbean Yi, Sandip Kundu, Sangwook Cho, Sungju Park
2010	—	`conf`	A mask double patterning technique using litho simulation by wavelet transform. ACM Great Lakes Symposium on VLSI Rance Rodrigues, Sandip Kundu
2010	—	`conf`	A model to exploit power-performance efficiency in superscalar processors via structure resizing. ACM Great Lakes Symposium on VLSI Omer Khan, Sandip Kundu
2010	—	`conf`	A self-adaptive scheduler for asymmetric multi-cores. ACM Great Lakes Symposium on VLSI Omer Khan, Sandip Kundu
2010	C	`conf`	A study on performance benefits of core morphing in an asymmetric multicore processor. ICCD Anup Das, Rance Rodrigues, Israel Koren, Sandip Kundu
2010	J	`jnl`	An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects. IEEE Trans. Computers Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu
2010	J	`jnl`	BIST to Detect and Characterize Transient and Parametric Failures. IEEE Des. Test Comput. Alodeep Sanyal, Syed M. Alam, Sandip Kundu
2010	A	`conf`	Modeling the impact of process variation on resistive bridge defects. ITC S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu
2010	J	`jnl`	On ATPG for Multiple Aggressor Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kunal P. Ganeshpure, Sandip Kundu
2010	J	`jnl`	On-Chip Support for NoC-Based SoC Debugging. IEEE Trans. Circuits Syst. I Regul. Pap. Hyunbean Yi, Sungju Park, Sandip Kundu
2010	Misc	`conf`	Optical Lithography Simulation with Focus Variation using Wavelet Transform. VLSI Design Rance Rodrigues, Sandip Kundu
2010	A	`conf`	Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. ITC Rance Rodrigues, Sandip Kundu, Omer Khan
2010	—	`conf`	TURBONFS: turbo nand flash search. ACM Great Lakes Symposium on VLSI Shruti Vyas, Aswin Sreedhar, Sandip Kundu
2010	J	`jnl`	Test pattern generation for droop faults. IET Comput. Digit. Tech. Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey
2010	J	`jnl`	Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. IEEE Trans. Computers Omer Khan, Sandip Kundu
2009	—	`conf`	A Process Variation Tolerant Self-Compensating Sense Amplifier Design. ISVLSI Aarti Choudhary, Sandip Kundu
2009	—	`conf`	A process variation tolerant self-compensating FinFET based sense amplifier design. ACM Great Lakes Symposium on VLSI Aarti Choudhary, Sandip Kundu
2009	A	`conf`	A self-adaptive system architecture to address transistor aging. DATE Omer Khan, Sandip Kundu
2009	—	`conf`	A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits. ACM Great Lakes Symposium on VLSI Alodeep Sanyal, Abhisek Pan, Sandip Kundu
2009	—	`conf`	A study on impact of loading effect on capacitive crosstalk noise. ISQED Alodeep Sanyal, Abhisek Pan, Sandip Kundu
2009	A	`conf`	A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. DATE Kelageri Nagaraj, Sandip Kundu
2009	Misc	`conf`	An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. VLSI Design Kunal P. Ganeshpure, Sandip Kundu
2009	J	`jnl`	An Improved Soft-Error Rate Measurement Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
2009	A	`conf`	Hardware/software co-design architecture for thermal management of chip multiprocessors. DATE Omer Khan, Sandip Kundu
2009	A	`conf`	Improving yield and reliability of chip multiprocessors. DATE Abhisek Pan, Omer Khan, Sandip Kundu
2009	A	`conf`	On linewidth-based yield analysis for nanometer lithography. DATE Aswin Sreedhar, Sandip Kundu
2009	—	`conf`	On process variation tolerant low cost thermal sensor design in 32nm CMOS technology. ACM Great Lakes Symposium on VLSI Spandana Remarsu, Sandip Kundu
2009	C	`conf`	Optical lithography simulation using wavelet transform. ICCD Rance Rodrigues, Aswin Sreedhar, Sandip Kundu
2009	—	`conf`	Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. HiPEAC Omer Khan, Sandip Kundu
2009	—	`conf`	Process variation mitigation via post silicon clock tuning. ACM Great Lakes Symposium on VLSI Kelageri Nagaraj, Sandip Kundu
2009	—	`conf`	Reducing temperature variability by routing heat pipes. ACM Great Lakes Symposium on VLSI Kunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker
2009	J	`jnl`	Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip. J. Low Power Electron. Rishad Ahmed Shafik, Bashir M. Al-Hashimi, Sandip Kundu, Alireza Ejlali
2009	C	`conf`	Statistical timing analysis based on simulation of lithographic process. ICCD Aswin Sreedhar, Sandip Kundu
2008	C	`conf`	A Built-In Self-Test Scheme for Soft Error Rate Characterization. IOLTS Alodeep Sanyal, Syed M. Alam, Sandip Kundu
2008	—	`conf`	A Built-in Test and Characterization Method for Circuit Marginality Related Failures. ISQED Alodeep Sanyal, Sandip Kundu
2008	—	`conf`	A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC. ATS Hyunbean Yi, Sungju Park, Sandip Kundu
2008	—	`conf`	A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. DFT Abhisek Pan, James W. Tschanz, Sandip Kundu
2008	A	`conf`	A framework for predictive dynamic temperature management of microprocessor systems. ICCAD Omer Khan, Sandip Kundu
2008	A	`conf`	An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements. ITC Kelageri Nagaraj, Sandip Kundu
2008	—	`conf`	Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing. DFT Hyunbean Yi, Sandip Kundu
2008	J	`jnl`	Lithography Simulation Basics and a Study on Impact of Lithographic Process Window on Gate and Path Delays. J. Low Power Electron. Aswin Sreedhar, Sandip Kundu
2008	C	`conf`	Modeling and analysis of non-rectangular transistors caused by lithographic distortions. ICCD Aswin Sreedhar, Sandip Kundu
2008	Misc	`conf`	On Common-Mode Skewed-Load and Broadside Tests. VLSI Design Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2008	J	`jnl`	On Composite Leakage Current Maximization. J. Electron. Test. Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu
2008	J	`jnl`	On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
2008	A	`conf`	On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. DATE Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu
2008	A	`conf`	Statistical Yield Modeling for Sub-wavelength Lithography. ITC Aswin Sreedhar, Sandip Kundu
2008	C	`conf`	The Guiding Light for Chip Testing. DDECS Sandip Kundu
2007	C	`conf`	A Study on Impact of Leakage Current on Dynamic Power. ISCAS Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu
2007	C	`conf`	Accelerating Soft Error Rate Testing Through Pattern Selection. IOLTS Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
2007	Misc	`conf`	An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. VLSI Design Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu
2007	J	`jnl`	Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems". IEEE Trans. Very Large Scale Integr. Syst. Dimitris Gizopoulos, Robert C. Aitken, Sandip Kundu
2007	A	`conf`	Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. DATE Kunal P. Ganeshpure, Sandip Kundu
2007	A	`conf`	On ATPG for multiple aggressor crosstalk faults in presence of gate delays. ITC Kunal P. Ganeshpure, Sandip Kundu
2007	—	`conf`	On Accelerating Soft-Error Detection by Targeted Pattern Generation. ISQED Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
2007	C	`conf`	On Derating Soft Error Probability Based on Strength Filtering. IOLTS Alodeep Sanyal, Sandip Kundu
2007	A*	`conf`	On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. DAC Ashesh Rastogi, Wei Chen, Sandip Kundu
2007	C	`conf`	On modeling impact of sub-wavelength lithography on transistors. ICCD Aswin Sreedhar, Sandip Kundu
2007	J	`jnl`	Power Droop Testing. IEEE Des. Test Comput. Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
2006	C	`conf`	A Pattern Generation Technique for Maximizing Power Supply Currents. ICCD Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu
2006	A	`conf`	A design for failure analysis (DFFA) technique to ensure incorruptible signatures. DATE Sandip Kundu
2006	C	`conf`	An Improved Technique for Reducing False Alarms Due to Soft Errors. IOLTS Sandip Kundu, Ilia Polian
2006	C	`conf`	Power Droop Testing. ICCD Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
2006	J	`jnl`	TTTC technical forum honoring Sudhakar M. Reddy. IEEE Des. Test Comput. Sandip Kundu
2006	Misc	`conf`	Test Pattern Generation for Power Supply Droop Faults. VLSI Design Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu
2005	—	`conf`	On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Asian Test Symposium Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker
2005	J	`jnl`	On modeling crosstalk faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti
2005	B	`conf`	Path-oriented transition fault test generation considering operating conditions. ETS Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2005	Misc	`conf`	Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker
2005	A	`conf`	Transient fault characterization in dynamic noisy environments. ITC Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker
2004	A	`conf`	A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang
2004	J	`jnl`	ITC 2003 Roundtable: Design for Manufacturability. IEEE Des. Test Comput. Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker
2004	J	`jnl`	Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
2004	J	`jnl`	On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2004	J	`jnl`	Pitfalls of hierarchical fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sandip Kundu
2004	A	`conf`	Static statistical timing analysis for latch-based pipeline designs. ICCAD Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu
2004	A	`conf`	Trends in manufacturing test methods and their implications. ITC Sandip Kundu, T. M. Mak, Rajesh Galivanche
2003	A	`conf`	Circuit and Platform Design Challenges in Technologies beyond 90nm. DATE Bill Grundmann, Rajesh Galivanche, Sandip Kundu
2003	A	`conf`	On Modeling Cross-Talk Faults. DATE Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti
2003	—	`conf`	On path selection for delay fault testing considering operating conditions [logic IC testing]. ETW Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003	A	`conf`	On the Characterization of Hard-to-Detect Bridging Faults. DATE Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2003	A	`conf`	On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2002	A*	`conf`	On output response compression in the presence of unknown output values. DAC Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy
2001	A*	`conf`	Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
2001	Misc	`conf`	On Fault-Simulation Through Embedded Memories On Large Industrial Designs. VLSI Design Sitaram Yadavalli, Sandip Kundu
2001	J	`jnl`	Test Challenges in Nanometer Technologies. J. Electron. Test. Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche
2000	—	`conf`	Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu
2000	—	`conf`	Test challenges in nanometer technologies. ETW Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche
1999	C	`conf`	On Detecting Bridges Causing Timing Failures. ICCD Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu
1998	A	`conf`	GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. ITC Sandip Kundu
1998	—	`conf`	IDDQ Defect Detection in Deep Submicron CMOS ICs. Asian Test Symposium Sandip Kundu
1998	—	`conf`	Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). ASP-DAC Anirudh Devgan, Sandip Kundu
1997	—	`conf`	Inductance analysis of on-chip interconnects [deep submicron CMOS]. ED&TC Sandip Kundu, Uttam Ghoshal
1997	A	`conf`	Timing analysis and optimization: from devices to systems (tutorial). ICCAD Anirudh Devgan, Leon Stok, Sandip Kundu
1996	J	`jnl`	Self-Checking Comparator with One Periodic Output. IEEE Trans. Computers Sandip Kundu, Egor S. Sogomonyan, Michael Gössel, Steffen Tarnick
1995	J	`jnl`	On Construction of Non-systematic t-Symmetric Error Correcting/All Unidirectional Error Detecting Codes. IEICE Trans. Inf. Syst. Sandip Kundu
1995	—	`conf`	Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri
1994	J	`jnl`	An efficient technique for obtaining unate implementation of functions through input encoding. Integr. Sandip Kundu
1994	J	`jnl`	An incremental algorithm for identification of longest (shortest) paths. Integr. Sandip Kundu
1994	J	`jnl`	Diagnosing scan chain faults. IEEE Trans. Very Large Scale Integr. Syst. Sandip Kundu
1994	J	`jnl`	Highly Reliable Symmetric Networks. IEEE Trans. Parallel Distributed Syst. Leendert M. Huisman, Sandip Kundu
1994	A	`conf`	Incremental synthesis. ICCAD Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain
1994	A*	`conf`	Microprocessor Testing: Which Technique is Best? (Panel). DAC Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther
1994	C	`conf`	Multifault Testable Circuits Based on Binary Parity Diagrams. ICCD Sandip Kundu
1993	A	`conf`	Design of Scan-Based Path-Delay-Testable Sequential Circuits. ITC Ankan K. Pramanick, Sandip Kundu
1993	Misc	`conf`	On diagnosis of faults in a scan-chain. VTS Sandip Kundu
1993	Misc	`conf`	Testability preserving Boolean transforms for logic synthesis. VTS Sandip Kundu, Ankan K. Pramanick
1992	A	`conf`	A Small Test Generator for Large Designs. ITC Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
1991	J	`jnl`	Design of robustly testable combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
1991	—	`conf`	Symbolic implication in test generation. EURO-DAC Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar
1991	—	`conf`	Synthesis of fully testable sequential machines. EURO-DAC Roy Thomas, Sandip Kundu
1990	J	`jnl`	Embedded Totally Self-Checking Checkers: A Practical Design. IEEE Des. Test Comput. Sandip Kundu, Sudhakar M. Reddy
1990	J	`jnl`	On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. IEEE Trans. Computers Sandip Kundu, Sudhakar M. Reddy
1990	J	`jnl`	Robust tests for parity trees. J. Electron. Test. Sandip Kundu, Sudhakar M. Reddy
1989	C	`conf`	Design of TSC checkers for implementation in CMOS technology. ICCD Sandip Kundu, Sudhakar M. Reddy
1989	J	`jnl`	Design of multioutput CMOS combinational logic circuits for robust testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sandip Kundu
1988	A	`conf`	On the design of robust multiple fault testable CMOS combinational logic circuits. ICCAD Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha
1988	—	`conf`	On the design of robust testable CMOS combinational logic circuits. FTCS Sandip Kundu, Sudhakar M. Reddy
1988	A	`conf`	Robust Tests for Parity Trees. ITC Sandip Kundu, Sudhakar M. Reddy