Sandeep Miryala

26 papers A 2C 2Misc 1Journal 6Unranked 14

Year	Rank	Type	Title / Venue / Authors
2023	Misc	`conf`	An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	J	`jnl`	A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM IEEE Trans. Very Large Scale Integr. Syst. Liang Fang, Xianshan Wen, Tao Fu, Guanhua Wang, Sandeep Miryala, Tiehui Ted Liu, Ping Gui
2022	C	`conf`	A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	J	`jnl`	An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	—	`conf`	Design and Challenges of Edge Computing ASICs on Front-End Electronics. ISQED Sandeep Miryala, Gabriella Carini, Grzegorz Deptuch, Jin Huang, Srinivas Katkoori, Piotr Maj, Soumyajit Mandal, Yihui Ren, Md. Adnan Zaman
2022	—	`conf`	Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array. PRIME Dominik Gorni, Grzegorz Deptuch, Sandeep Miryala
2022	—	`conf`	Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications. ISQED Sandeep Miryala, Md. Adnan Zaman, Sandeep Mittal, Yihui Ren, Grzegorz Deptuch, Gabriella Carini, Sioan Zohar, Shinjae Yoo, Jack Fried, Jin Huang, Srinivas Katkoori
2020	—	`conf`	A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process. UEMCON Vamshi Manthena, Sandeep Miryala, Grzegorz Deptuch, Gabriella Carini
2017	J	`jnl`	Schottky-barrier graphene nanoribbon field-effect transistors-based field-programmable gate array's configurable logic block and routing switch. IET Circuits Devices Syst. Sayed Ali Seif Kashani, Hossein Karimiyan Alidash, Sandeep Miryala
2016	—	`conf`	A novel energy-efficient self-correcting methodology employing INWE. SMACD Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu
2015	—	`conf`	Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. ACM Great Lakes Symposium on VLSI Roberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2015	—	`conf`	Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. ACM Great Lakes Symposium on VLSI Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2015	J	`jnl`	Ultra-low power circuits using graphene p-n junctions and adiabatic computing. Microprocess. Microsystems Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2014	—	`—`	CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems. Sandeep Miryala
2014	J	`jnl`	Modeling of Physical Defects in PN Junction Based Graphene Devices. J. Electron. Test. Sandeep Miryala, Matheus Oleiro, Letícia Maria Bolzani Pöhls, Andrea Calimera, Enrico Macii, Massimo Poncino
2014	J	`jnl`	Row-based body-bias assignment for dynamic thermal clock-skew compensation. Microelectron. J. Valerio Tenace, Sandeep Miryala, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2014	C	`conf`	Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. DSD Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2013	A	`conf`	A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. DATE Sandeep Miryala, Mehrdad Montazeri, Andrea Calimera, Enrico Macii, Massimo Poncino
2013	—	`conf`	An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. ISQED Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand
2013	—	`conf`	Delay model for reconfigurable logic gates based on graphene PN-junctions. ACM Great Lakes Symposium on VLSI Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2013	—	`conf`	Exploration of different implementation styles for graphene-based reconfigurable gates. ICICDT Sandeep Miryala, Andrea Calimera, Massimo Poncino, Enrico Macii
2013	—	`conf`	Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. LATW Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino, Letícia Maria Veiras Bolzani Poehls
2013	—	`conf`	Power modeling and characterization of Graphene-based logic gates. PATMOS Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2012	A	`conf`	IR-drop analysis of graphene-based power distribution networks. DATE Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino
2012	—	`conf`	NBTI effects on tree-like clock distribution networks. ACM Great Lakes Symposium on VLSI Wei Liu, Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino
2011	—	`conf`	Efficient nanoscale VLSI standard cell library characterization using a novel delay model. ISQED Sandeep Miryala, Baljit Kaur, Bulusu Anand, Sanjeev Manhas