Sandeep Kumar Goel

63 papers A* 2A 25B 6Misc 4Journal 13Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	A Novel Omnidirectional 3D Test Access Architecture for Advanced System-on-Wafer (SoW) Applications. ITC Hiroyuki Iwata, Sandeep Kumar Goel, Ankita Patidar, Fumiaki Takashima, Frank Lee
2025	A	`conf`	Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging ITC Partho Bhoumik, Arjun Chaudhuri, Sandeep Kumar Goel, Krishnendu Chakrabarty
2025	J	`jnl`	Guest Editorial 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test - Part I. IEEE J. Emerg. Sel. Topics Circuits Syst. Qinfen Hao, Kuan-Neng Chen, Sandeep Kumar Goel, Hai Li, Erik Jan Marinissen
2025	J	`jnl`	Guest Editorial: 2.5-D/3-D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test - Part II. IEEE J. Emerg. Sel. Topics Circuits Syst. Qinfen Hao, Kuan-Neng Chen, Sandeep Kumar Goel, Hai Li, Erik Jan Marinissen
2025	A	`conf`	Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D Stack. ITC Sandeep Kumar Goel, Ankita Patidar, Stanley John, Frank Lee, Min-Jer Wang, Daniel F. J. Yang, Yervant Zorian, Manish Arora, Firooz Massoudi, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Narasimhalu Raju, Gurgen Harutyunyan, Grigor Tshagharyan, Vahagn Hovakimyan, Arman Karagyozyan, Alvina Manucharyan
2025	A	`conf`	Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost. ITC Sandeep Kumar Goel, Ankita Patidar, Yue Tian, Frank Lee
2024	A	`conf`	Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests. ITC Sandeep Kumar Goel, Moiz Khan, Ankita Patidar, Frank Lee, Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, Manish Arora
2024	A	`conf`	Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard. ITC Sandeep Kumar Goel, Ankita Patidar, Moiz Khan, Frank Lee, Anshuman Chandra, Martin Keim, Naim Lemar, Jonathan Gaudet, Quoc Phan, Vidya Neerkundar
2024	B	`conf`	Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact. ETS Sandeep Kumar Goel, Ankita Patidar, Frank Lee
2023	A	`conf`	A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation. ITC Anshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora
2022	—	`conf`	Challenges and Solutions for 3D Fabric: A Foundry Perspective. ISPD Sandeep Kumar Goel
2022	Misc	`conf`	Innovative Practices Track: Test of 3D ICs & Chiplets. VTS Sandeep Kumar Goel, Sandeep Pendharkar, Chunsheng Liu
2020	J	`jnl`	A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. IEEE J. Solid State Circuits Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee
2019	—	`conf`	A 7nm 4GHz Arm VLSI Circuits Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee
2015	J	`jnl`	Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption. IEEE Trans. Computers Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen
2015	A	`conf`	Efficient observation-point insertion for diagnosability enhancement in digital circuits. ITC Zipeng Li, Sandeep Kumar Goel, Frank Lee, Krishnendu Chakrabarty
2014	—	`ch.`	Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits Sandeep Kumar Goel, Krishnendu Chakrabarty
2014	—	`conf`	Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS VLSI-DAT Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee
2014	—	`ch.`	Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits Sandeep Kumar Goel, Narendra Devta-Prasanna
2014	J	`jnl`	Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2014	—	`ch.`	Small-Delay Defect Coverage Metrics. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits Narendra Devta-Prasanna, Sandeep Kumar Goel
2014	—	`book`	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. Sandeep Kumar Goel, Krishnendu Chakrabarty
2013	A	`conf`	Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
2012	A	`conf`	DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
2012	A	`conf`	EDA solutions to new-defect detection in advanced process technologies. DATE Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl
2012	A	`conf`	Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track. ICCAD Sandeep Kumar Goel
2011	—	`conf`	Automation of 3D-DfT Insertion. Asian Test Symposium Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel
2011	B	`conf`	DfT Architecture for 3D-SICs with Multiple Towers. ETS Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	—	`conf`	Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	A	`conf`	Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu
2011	J	`jnl`	Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree
2010	—	`conf`	Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. Asian Test Symposium Sandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, Mohammad Tehranipoor
2010	B	`conf`	Test-architecture optimization for TSV-based 3D stacked ICs. ETS Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree
2009	A	`conf`	Accurate measurement of small delay defect coverage of test patterns. ITC Narendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy
2009	Misc	`conf`	Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study. VTS Ritesh P. Turakhia, Mark Ward, Sandeep Kumar Goel, Brady Benware
2009	A	`conf`	Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. ITC Sandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward
2009	Misc	`conf`	Effective and Efficient Test Pattern Generation for Small Delay Defect. VTS Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia
2009	J	`jnl`	Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty
2007	J	`jnl`	Efficient testing and diagnosis of faulty power switches in SOCs. IET Comput. Digit. Tech. Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
2007	J	`jnl`	On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips CoRR Sandeep Kumar Goel, Erik Jan Marinissen
2006	A*	`conf`	Fault detection and diagnosis with parity trees for space compaction of test responses. DAC Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
2006	A	`conf`	Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2006	B	`conf`	Testing and Diagnosis of Power Switches in SOCs. ETS Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
2005	A	`conf`	On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. DATE Sandeep Kumar Goel, Erik Jan Marinissen
2005	B	`conf`	Test scheduling for modular SOCs in an abort-on-fail environment. ETS Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen
2004	A*	`conf`	Automatic generation of breakpoint hardware for silicon debug. DAC Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel
2004	A	`conf`	IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2004	A	`conf`	Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. DATE Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk
2004	B	`conf`	User-constrained test architecture design for modular SOC testing. ETS Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre
2003	J	`jnl`	A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. J. Electron. Test. Sandeep Kumar Goel, Erik Jan Marinissen
2003	—	`conf`	Control-aware test architecture design for modular SOC testing. ETW Sandeep Kumar Goel, Erik Jan Marinissen
2003	J	`jnl`	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. J. Electron. Test. Sandeep Kumar Goel, Bart Vermeulen
2003	A	`conf`	Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. DATE Sandeep Kumar Goel, Erik Jan Marinissen
2003	J	`jnl`	SOC test architecture design for efficient utilization of test bandwidth. ACM Trans. Design Autom. Electr. Syst. Sandeep Kumar Goel, Erik Jan Marinissen
2002	—	`conf`	A novel test time reduction algorithm for test architecture design for core-based system chips. ETW Sandeep Kumar Goel, Erik Jan Marinissen
2002	Misc	`conf`	Cluster-Based Test Architecture Design for System-on-Chip. VTS Sandeep Kumar Goel, Erik Jan Marinissen
2002	A	`conf`	Core-Based Scan Architecture for Silicon Debug. ITC Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
2002	—	`conf`	Data invalidation analysis for scan-based debug on multiple-clock system chips. ETW Sandeep Kumar Goel, Bart Vermeulen
2002	J	`jnl`	Design for Debug: Catching Design Errors in Digital Chips. IEEE Des. Test Comput. Bart Vermeulen, Sandeep Kumar Goel
2002	A	`conf`	Effective and Efficient Test Architecture Design for SOCs. ITC Sandeep Kumar Goel, Erik Jan Marinissen
2002	A	`conf`	Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ITC Sandeep Kumar Goel, Bart Vermeulen
2002	A	`conf`	Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
2000	A	`conf`	Wrapper design for embedded core test. ITC Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel