Samuel Riedel

36 papers A* 2A 7C 1Journal 22Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link.
CoRR
Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini
2025 J jnl
A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN.
CoRR
Yichao Zhang, Marco Bertuletti, Sergio Mazzola, Samuel Riedel, Luca Benini
2025 J jnl
Area Comparison of CHERIoT and PMP in Ibex.
CoRR
Samuel Riedel, Marno van der Maas, John Thomson, Andreas Kurth, Pirmin Vogel
2025 J jnl
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC.
IEEE Trans. Very Large Scale Integr. Syst.
Sudipta Das, Samuel Riedel, Mohamed Naeim, Moritz Brunion, Marco Bertuletti, Luca Benini, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic
2025 A* conf
Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access Networks.
DAC
Marco Bertuletti, Yichao Zhang, Mahdi Abdollahpour, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini
2025 — conf
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication.
IWASI
Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini
2025 J jnl
Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication.
CoRR
Samuel Riedel, Yichao Zhang, Marco Bertuletti, Luca Benini
2025 J jnl
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Matteo Perotti, Samuel Riedel, Matheus A. Cavalcante, Luca Benini
2025 J jnl
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link.
IEEE Trans. Computers
Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini
2024 C conf
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs.
ISCAS
Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic
2024 J jnl
A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR.
CoRR
Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini
2024 J jnl
A High-Performance, Energy-Efficient Modular DMA Engine Architecture.
IEEE Trans. Computers
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini
2024 J jnl
Enabling Efficient Hybrid Systolic Computation in Shared L1-Memory Manycore Clusters.
CoRR
Sergio Mazzola, Samuel Riedel, Luca Benini
2024 J jnl
Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters.
IEEE Trans. Very Large Scale Integr. Syst.
Sergio Mazzola, Samuel Riedel, Luca Benini
2024 J jnl
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
2024 A conf
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation.
DATE
Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini
2024 J jnl
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation.
CoRR
Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini
2024 — conf
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios.
ACM Great Lakes Symposium on VLSI
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
2024 J jnl
TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios.
CoRR
Yichao Zhang, Marco Bertuletti, Samuel Riedel, Matheus A. Cavalcante, Alessandro Vanelli-Coralli, Luca Benini
2023 J jnl
A High-performance, Energy-efficient Modular DMA Engine Architecture.
CoRR
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini
2023 — conf
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.
SAMOS
Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
2023 J jnl
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster.
CoRR
Marco Bertuletti, Samuel Riedel, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini
2023 A conf
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster.
DATE
Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini
2023 J jnl
MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory.
IEEE Trans. Computers
Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini
2023 J jnl
MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory.
CoRR
Samuel Riedel, Matheus A. Cavalcante, Renzo Andri, Luca Benini
2023 — conf
MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS.
ICECS
Samuel Riedel, Matheus A. Cavalcante, Manos Frouzakis, Domenic Wüthrich, Enis Mustafa, Arlind Billa, Luca Benini
2023 J jnl
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency.
CoRR
Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini
2022 A conf
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs.
ISLPED
Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
2022 A conf
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.
DATE
Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
2022 A conf
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters.
ICCAD
Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
2022 J jnl
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters.
CoRR
Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini
2021 A conf
Banshee: A Fast LLVM-Based RISC-V Binary Translator.
ICCAD
Samuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini
2021 J jnl
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.
CoRR
Matheus A. Cavalcante, Anthony Agnesina, Samuel Riedel, Moritz Brunion, Alberto García-Ortiz, Dragomir Milojevic, Francky Catthoor, Sung Kyu Lim, Luca Benini
2021 A conf
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect.
DATE
Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini
2020 A* conf
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor.
DAC
Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini
2020 J jnl
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect.
CoRR
Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini