Samuel Naffziger

34 papers A* 2A 2Misc 1Journal 13Unranked 16

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	2.1 AMD Instinct MI350 Series GPUs: CDNA 4-Based 3D-Stacked 3nm XCDs and 6nm IODs for AI Applications. ISSCC Ramasamy Adaikkalavan, Alan Smith, Teja Singh, Sundar Rangarajan, Eric Chapman, Samuel Naffziger, Subramaniam Maiyuran, Candy Chen, Sriram Sundaram, Mark Silla, Duncan Law, Kathy Hoover, Samuel Lipson, Kevin Duda, Vinay Parthasarathy, Deepesh John, Hanish Vemulapalli, Srinivas Pavan Kumar Gade
2025	J	`jnl`	Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator. IEEE Micro Alan Smith, Gabriel H. Loh, Samuel Naffziger, John J. Wuu, Nathan Kalyanasundharam, Eric Chapman, Raja Swaminathan, Tyrone Huang, Wonjun Jung, Alexander Kaganov, Hugh McIntyre, Ramon Mangaser
2024	—	`conf`	AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. VLSI Technology and Circuits Alan Smith, Gabriel H. Loh, John J. Wuu, Samuel Naffziger, Tyrone Huang, Hugh McIntyre, Ramon Mangaser, Wonjun Jung, Raja Swaminathan
2024	A*	`conf`	Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. ISCA Alan Smith, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, Nathan Kalyanasundharam, Vamsi Alla, Nicholas Malaya, Joseph L. Greathouse, Eric Chapman, Raja Swaminathan
2022	—	`conf`	3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. ISSCC John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger
2021	—	`conf`	A New Era of Tailored Computing. VLSI Circuits Mark Papermaster, Stephen Kosonocky, Gabriel H. Loh, Samuel Naffziger
2021	A*	`conf`	Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product. ISCA Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, Sean White
2021	—	`conf`	SE1: What Technologies Will Shape the Future of Computing? ISSCC Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag
2021	A	`conf`	Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. DATE Gabriel H. Loh, Samuel Naffziger, Kevin Lepak
2020	—	`conf`	2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. ISSCC Samuel Naffziger, Kevin Lepak, Milam Paraschou, Mahesh Subramony
2020	—	`conf`	8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs. ISSCC Sal Dasgupta, Teja Singh, Ashish Jain, Samuel Naffziger, Deepesh John, Chetan Bisht, Pradeep Jayaraman
2019	J	`jnl`	"Zeppelin": An SoC for Multichip Architectures. IEEE J. Solid State Circuits Thomas Burd, Noah Beck, Sean White, Milam Paraschou, Nathan Kalyanasundharam, Gregg Donley, Alan Smith, Larry Hewitt, Samuel Naffziger
2018	—	`conf`	'Zeppelin': An SoC for multichip architectures. ISSCC Noah Beck, Sean White, Milam Paraschou, Samuel Naffziger
2018	J	`jnl`	Zen: An Energy-Efficient High-Performance × 86 Core. IEEE J. Solid State Circuits Teja Singh, Alex Schaefer, Sundar Rangarajan, Deepesh John, Carson Henrion, Russell Schreiber, Miguel Rodriguez, Stephen Kosonocky, Samuel Naffziger, Amy Novak
2017	J	`jnl`	Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. IEEE J. Solid State Circuits Sriram Sundaram, Aaron Grenat, Samuel Naffziger, Tom Burd, Stephen Kosonocky, Steven Liepe, Ravinder Rachala, Miguel Rodriguez, Michael Austin, Sriram Sambamurthy
2016	—	`conf`	4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. ISSCC Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger
2016	Misc	`conf`	Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. VLSID Sriram Sundaram, Sriram Sambamurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger
2016	J	`jnl`	Carrizo: A High Performance, Energy Efficient 28 nm APU. IEEE J. Solid State Circuits Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox
2016	J	`jnl`	Energy-Efficient Graphics and Multimedia in 28-nm Carrizo Accelerated Processing Unit. IEEE Micro Guhan Krishnan, Dan Bouvier, Samuel Naffziger
2016	A	`conf`	Unified Power Frequency Model Framework. ISLPED Sriram Sundaram, Warren He, Sriram Sambamurthy, Aaron Grenat, Steven Liepe, Samuel Naffziger
2015	—	`conf`	4.8 A 28nm x86 APU optimized for power and area efficiency. ISSCC Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White
2015	J	`jnl`	Hot Chips 26 [Guest editors' introduction]. IEEE Micro Samuel Naffziger, Guri Sohi
2015	J	`jnl`	Steamroller Module and Adaptive Clocking System in 28 nm CMOS. IEEE J. Solid State Circuits Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White
2014	—	`conf`	5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. ISSCC Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger
2014	—	`conf`	Welcome program chairs. Hot Chips Symposium Samuel Naffziger, Guri Sohi
2013	J	`jnl`	Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger
2012	—	`conf`	Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules. CICC Steve J. Dillen, Donald A. Priore, Aaron Horiuchi, Samuel Naffziger
2012	J	`jnl`	Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. IEEE J. Solid State Circuits Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh
2012	—	`conf`	Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger
2011	—	`conf`	Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. ISSCC Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox
2010	—	`conf`	A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm ISSCC Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon
2006	J	`jnl`	A 90-nm variable frequency clock system for a power-managed itanium architecture processor. IEEE J. Solid State Circuits Tim C. Fischer, Jayen Desai, Bruce Andrew Doyle, Samuel Naffziger, Ben Patella
2006	J	`jnl`	Power and temperature control on a 90-nm Itanium family processor. IEEE J. Solid State Circuits Rich McGowen, Christopher Poirier, Chris Bostak, Jim Ignowski, Mark Millican, Warren H. Parks, Samuel Naffziger
2006	J	`jnl`	The implementation of a 2-core, multi-threaded itanium family processor. IEEE J. Solid State Circuits Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz