Samira Ataei

12 papers A 1C 1Journal 2Unranked 8
YearRankTypeTitle / Venue / Authors
2021 J jnl
An Open-Source EDA Flow for Asynchronous Logic.
IEEE Des. Test
Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali
2020 — conf
Shared-Staticizer for Area-Efficient Asynchronous Circuits.
ASYNC
Samira Ataei, Rajit Manohar
2019 — conf
AMC: An Asynchronous Memory Compiler.
ASYNC
Samira Ataei, Rajit Manohar
2018 J jnl
A 64 kB Approximate SRAM Architecture for Low-Power Video Applications.
IEEE Embed. Syst. Lett.
Samira Ataei, James E. Stine
2018 — conf
A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications.
SoCC
Samira Ataei, James E. Stine
2017 — conf
A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time.
ACM Great Lakes Symposium on VLSI
Samira Ataei, James E. Stine
2017 — conf
A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS.
MWSCAS
Samira Ataei, Matthew Gaalswyk, James E. Stine
2017 — conf
WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm.
MSE
Rabin Thapa, Samira Ataei, James E. Stine
2016 C conf
A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS.
ICCD
Samira Ataei, James E. Stine, Matthew R. Guthaus
2016 A conf
OpenRAM: an open-source memory compiler.
ICCAD
Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar
2015 — conf
A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation.
IGSC
Samira Ataei, James E. Stine
2015 — conf
Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers.
ACM Great Lakes Symposium on VLSI
Samira Ataei, James E. Stine