Samir Roy

26 papers Misc 5Journal 11Unranked 10
YearRankTypeTitle / Venue / Authors
2023 J jnl
ECKM: An improved K-means clustering based on computational geometry.
Expert Syst. Appl.
Tuhin Kr. Biswas, Kinsuk Giri, Samir Roy
2019 J jnl
Automatic short answer grading using rough concept clusters.
Int. J. Adv. Intell. Paradigms
Udit Kr. Chakraborty, Debanjan Konar, Samir Roy, Sankhayan Choudhury
2018 J jnl
A neural network-based intelligent cognitive state recognizer for confidence-based e-learning system.
Neural Comput. Appl.
Suman Bhattacharya, Samir Roy, Sankhayan Chowdhury
2018 J jnl
An effective e-learning system through learners' scaffolding.
Int. J. Adv. Intell. Paradigms
Suman Bhattacharya, Sankhayan Chowdhury, Samir Roy
2017 J jnl
A Fuzzy Indiscernibility Based Measure of Distance between Semantic Spaces Towards Automatic Evaluation of Free Text Answers.
Int. J. Uncertain. Fuzziness Knowl. Based Syst.
Udit Kr. Chakraborty, Samir Roy, Sankhayan Choudhury
2016 J jnl
Intelligent fuzzy spelling evaluator for e-Learning systems.
Educ. Inf. Technol.
Udit Kr. Chakraborty, Debanjan Konar, Samir Roy, Sankhayan Choudhury
2014 — conf
Semantic Similarity Based Approach for Automatic Evaluation of Free Text Answers Using Link Grammar.
T4E
Udit Kr. Chakraborty, Rashmi Gurung, Samir Roy
2013 Misc conf
Online Recommendation of Learning Path for an E-Learner under Virtual University.
ICDCIT
Prasenjit Basu, Suman Bhattacharya, Samir Roy
2011 — conf
Fuzzy Automata Inspired Intelligent Assesment of Learning Achievement.
IICAI
Udit Kr. Chakraborty, Samir Roy
2006 — conf
Minority Gate Oriented Logic Design with Quantum-Dot Cellular Automata.
ACRI
Samir Roy, Biswajit Saha
2006 J jnl
Understanding the porosity dependence of heat flux through glass fiber insulation.
Math. Comput. Model.
Samir Roy, Michael Junk, S. Sundar
2005 J jnl
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area.
J. Electron. Test.
Biplab K. Sikdar, Samir Roy, Debesh K. Das
2005 Misc conf
Cellular Automata Based Test Structures with Logic Folding.
VLSI Design
Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das
2005 — conf
Synthesis of Testable Finite State Machine Through Decomposition.
Asian Test Symposium
Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das
2004 — conf
Cellular Automata Based Encompression Technology for Voice Data.
ACRI
Chandrama Shaw, Pradipta Maji, Sourav Saha, Biplab K. Sikdar, Samir Roy, Parimal Pal Chaudhuri
2003 J jnl
BHB: A Simple Knowledge-Based Scoring Function to Improve the Efficiency of Database Screening.
J. Chem. Inf. Comput. Sci.
Miklos Feher, Eugen Deretey, Samir Roy
2003 — conf
Efficient BIST design for sequential machines using FiF-FoF values in machine states.
ASP-DAC
Samir Roy, Ujjwal Maulik, Sanghamitra Bandyopadhyay, Subhadip Basu, Biplab Kumar Sikdar
2003 — conf
Evolutionary Approach to Solve the Complex-Triangle Elimination (CTE) Problem of VLSI Floor-planning.
IICAI
Samir Roy, Sanghamitra Bandyopadhyay, Ujjwal Maulik
2003 Misc conf
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines.
VLSI Design
Samir Roy, Ujjwal Maulik, Biplab K. Sikdar
2003 — conf
Power Conscious BIST Design for Sequential Circuits Using ghost-FSM.
Asian Test Symposium
Samir Roy, Biplab K. Sikdar
2002 — conf
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area.
ASP-DAC/VLSI Design
Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das
2001 — conf
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis.
Asian Test Symposium
Biplab K. Sikdar, Samir Roy, Debesh K. Das
1997 J jnl
KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
1996 J jnl
Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach.
IEEE Trans. Computers
Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
1995 Misc conf
Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.
VLSI Design
Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri
1993 Misc conf
Delay Fault Test Generation with Cellular Automata.
VLSI Design
Sukumar Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy