Samah Mohamed Saeed

47 papers A 6B 2C 5Misc 3Journal 18Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Undermining Quantum Circuit Obfuscation: Insights from Structural Analysis. HOST Donald Lushi, Samah Mohamed Saeed
2024	—	`conf`	Can ML-Based Reliability Models Span Quantum Hardware Boundaries? ISVLSI Georgios Ioannou, Gopika Kizhuvettil, Mohammad Walid Charrwi, Samah Mohamed Saeed
2024	J	`jnl`	Noise Adaptive Quantum Circuit Mapping Using Reinforcement Learning and Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vedika Saravanan, Samah Mohamed Saeed
2024	Misc	`conf`	Quantum Circuit Partitioning for Scalable Noise-Aware Quantum Circuit Re-Synthesis. QCE Mohammad Walid Charrwi, Georgios Ioannou, Ed Younis, Wibe Albert de Jong, Samah Mohamed Saeed
2024	—	`conf`	Time-Aware Re-Synthesis for Secure Quantum Systems. HOST Christian Rasmussen, Samah Mohamed Saeed
2023	J	`jnl`	Data-Driven Reliability Models of Quantum Circuit: From Traditional ML to Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vedika Saravanan, Samah Mohamed Saeed
2023	—	`conf`	Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation. ISVLSI Vedika Saravanan, Mohammad Walid Charrwi, Samah Mohamed Saeed
2022	A	`conf`	Graph Neural Networks for Idling Error Mitigation. ICCAD Vedika Saravanan, Samah Mohamed Saeed
2022	C	`conf`	Machine Learning for Quantum Hardware Performance Assessment. ICCD Vedika Saravanan, Samah Mohamed Saeed
2022	J	`jnl`	Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error Mitigation. CoRR Vedika Saravanan, Samah Mohamed Saeed
2022	J	`jnl`	Test Points for Online Monitoring of Quantum Circuits. ACM J. Emerg. Technol. Comput. Syst. Nikita Acharya, Miroslav Urbánek, Wibe A. de Jong, Samah Mohamed Saeed
2022	—	`conf`	Towards Yield Improvement for AI Accelerators: Analysis and Exploration. ISVLSI Mohammad Walid Charrwi, Huy Phan, Bo Yuan, Samah Mohamed Saeed
2021	—	`conf`	Automated Flag Qubit Insertion for Reliable Quantum Circuit Output. ISVLSI Nikita Acharya, Samah Mohamed Saeed
2021	—	`conf`	Decomposition-Based Watermarking of Quantum Circuits. ISQED Vedika Saravanan, Samah Mohamed Saeed
2021	B	`conf`	Test Data-Driven Machine Learning Models for Reliable Quantum Circuit Output. ETS Vedika Saravanan, Samah Mohamed Saeed
2020	A	`conf`	A Lightweight Approach to Detect Malicious/Unexpected Changes in the Error Rates of NISQ Computers. ICCAD Nikita Acharya, Samah Mohamed Saeed
2020	—	`conf`	An Attack on Quantum Circuits Based on the Error Rates of NISQ Systems and a Countermeasure. SVCC Nikita Acharya, Vedika Saravanan, Samah Mohamed Saeed
2020	—	`conf`	Analysis of Test Data Tampering Attack on Manufacturing Testing. DTIS Reginald Tetteh, Samah Mohamed Saeed
2020	J	`jnl`	On the Difficulty of Inserting Trojans in Reversible Computing Architectures. IEEE Trans. Emerg. Top. Comput. Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Kaijie Wu, Rolf Drechsler, Ramesh Karri
2019	J	`jnl`	CAD-Base: An Attack Vector into the Electronics Supply Chain. ACM Trans. Design Autom. Electr. Syst. Kanad Basu, Samah Mohamed Saeed, Christian Pilato, Mohammed Ashraf, Mohammed Thari Nabeel, Krishnendu Chakrabarty, Ramesh Karri
2019	J	`jnl`	Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits. ACM J. Emerg. Technol. Comput. Syst. Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Robert Wille, Ramesh Karri
2019	J	`jnl`	Locking the Design of Building Blocks for Quantum Circuits. ACM Trans. Embed. Comput. Syst. Samah Mohamed Saeed, Robert Wille, Ramesh Karri
2019	J	`jnl`	Reversible Circuits: IC/IP Piracy Attacks and Countermeasures. IEEE Trans. Very Large Scale Integr. Syst. Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Ramesh Karri
2018	A	`conf`	IC/IP piracy assessment of reversible logic. ICCAD Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
2017	J	`jnl`	A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications. IEEE Des. Test Samah Mohamed Saeed, Ozgur Sinanoglu
2017	C	`conf`	Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks. ICCD Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Robert Wille, Ramesh Karri
2017	J	`jnl`	On the Difficulty of Inserting Trojans in Reversible Computing Architectures. CoRR Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
2017	J	`jnl`	Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers. IEEE Trans. Emerg. Top. Comput. Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu
2017	J	`jnl`	Towards Reverse Engineering Reversible Logic. CoRR Samah Mohamed Saeed, Xiaotong Cui, Robert Wille, Alwin Zulehner, Kaijie Wu, Rolf Drechsler, Ramesh Karri
2016	A	`conf`	Activation of logic encrypted chips: Pre-test or post-test? DATE Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu
2016	Misc	`conf`	Thwarting timing attacks on NEMS relay based designs. VTS Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu
2015	J	`jnl`	Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
2015	C	`conf`	Timing attack on NEMS relay based design of AES. VLSI-SoC Samah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu
2014	J	`jnl`	Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing. IEEE Trans. Very Large Scale Integr. Syst. Samah Mohamed Saeed, Ozgur Sinanoglu
2014	A	`conf`	DfST: Design for secure testability. ITC Samah Mohamed Saeed
2014	—	`conf`	New scan attacks against state-of-the-art countermeasures and DFT. HOST Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri
2014	—	`conf`	Slack removal for enhanced reliability and trust. DTIS Abishek Ramdas, Samah Mohamed Saeed, Ozgur Sinanoglu
2014	A	`conf`	Test-mode-only scan attack and countermeasure for contemporary scan architectures. ITC Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri
2013	J	`jnl`	Expedited-compact architecture for average scan power reduction. IEEE Des. Test Samah Mohamed Saeed, Ozgur Sinanoglu
2013	—	`conf`	New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure. VLSI-SoC (Selected Papers) Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
2013	C	`conf`	New scan-based attack using only the test mode. VLSI-SoC Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri
2013	J	`jnl`	Predictive Techniques for Projecting Test Data Volume Compression. IEEE Trans. Very Large Scale Integr. Syst. Samah Mohamed Saeed, Ozgur Sinanoglu, Sobeeh Almukhaizim
2013	C	`conf`	Scan attack in presence of mode-reset countermeasure. IOLTS Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
2012	B	`conf`	DfT support for launch and capture power reduction in launch-off-capture testing. ETS Samah Mohamed Saeed, Ozgur Sinanoglu
2012	J	`jnl`	Multi-modal response compaction adaptive to x-density variation. IET Comput. Digit. Tech. Samah Mohamed Saeed, Ozgur Sinanoglu
2011	Misc	`conf`	Expedited response compaction for scan power reduction. VTS Samah Mohamed Saeed, Ozgur Sinanoglu
2010	—	`conf`	XOR-Based Response Compactor Adaptive to X-Density Variation. Asian Test Symposium Samah Mohamed Saeed, Ozgur Sinanoglu