Salvatore Levantino

143 papers C 16Journal 68Unranked 59

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	11.3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension. ISSCC Michele Rocco, Gabriele Zanoletti, Alessia Ceroni, Giacomo Tombolan, Gabriele Bè, Luca Ricci, Salvatore Levantino, Andrea Leonardo Lacaita, Luca Bertulessi, Carlo Samori, Andrea Giovanni Bonfanti
2026	—	`conf`	A -66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC. ISSCC Pietro Salvi, Michele Rossoni, Riccardo Moleri, Daniele Lodi Rizzini, Damiano Fagotti, Stefano Gallucci, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
2026	—	`conf`	A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving -62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise. ISSCC Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, Giovanni Rocco Trotta, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
2026	J	`jnl`	A Low-Jitter Fractional- N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology. IEEE J. Solid State Circuits Giacomo Castoro, Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Francesco Buccoleri, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2026	J	`jnl`	A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS. IEEE J. Solid State Circuits Daniele Lodi Rizzini, Francesco Tesolin, Michele Rossoni, Riccardo Moleri, Filippo Osio, Andrea Mazzanti, Andrea L. Lacaita, Simone Mattia Dartizio, Salvatore Levantino
2026	J	`jnl`	Frequency Synchronization Techniques for DC-DC Converters With Time-Based Control. IEEE Trans. Circuits Syst. II Express Briefs Alessandro Bertolini, Paolo Melillo, Mauro Leoncini, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
2025	—	`conf`	34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS. ISSCC Simone Mattia Dartizio, Giacomo Castoro, Stefano Gallucci, Michele Rossoni, Riccardo Moleri, Francesco Tesolin, Pietro Salvi, Saleh Karman, Andrea Leonardo Lacaita, Salvatore Levantino
2025	—	`conf`	34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning. ISSCC Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Simone Mattia Dartizio, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
2025	J	`jnl`	A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk. IEEE J. Solid State Circuits Luca Ricci, Gabriele Bè, Michele Rocco, Lorenzo Scaletti, Gabriele Zanoletti, Luca Bertulessi, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
2025	—	`conf`	A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3 CICC Gabriele Zanoletti, Gabriele Bè, Michele Rocco, Luca Ricci, Alessia Ceroni, Salvatore Levantino, Andrea Leonardo Lacaita, Luca Bertulessi, Andrea Bonfanti, Carlo Samori
2025	J	`jnl`	A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC. IEEE J. Solid State Circuits Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Andrea L. Lacaita, Salvatore Levantino
2025	J	`jnl`	A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators. IEEE J. Solid State Circuits Stefano Gallucci, Francesco Tesolin, Pietro Salvi, Daniele Lodi Rizzini, Riccardo Moleri, Francesco Buccoleri, Michele Rossoni, Giacomo Castoro, Carlo Samori, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
2025	J	`jnl`	A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC. IEEE J. Solid State Circuits Pietro Salvi, Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino
2024	—	`conf`	10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM. ISSCC Michele Rossoni, Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Riccardo Dell'Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
2024	—	`conf`	10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion. ISSCC Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
2024	J	`jnl`	A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars. IEEE J. Solid State Circuits Francesco Tesolin, Simone Mattia Dartizio, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2024	—	`conf`	A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector. CICC Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2024	—	`conf`	A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC. CICC Pietro Salvi, Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Andrea L. Lacaita, Salvatore Levantino
2024	—	`conf`	A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique. VLSI Technology and Circuits Riccardo Moleri, Simone Mattia Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
2024	J	`jnl`	A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions. IEEE Trans. Circuits Syst. I Regul. Pap. Paolo Melillo, Simone Zaffin, Mauro Leoncini, Alberto Brunero, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
2023	—	`conf`	A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS. VLSI Technology and Circuits Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Michele Rocco, Luca Bertulessi, Salvatore Levantino, Andrea L. Lacaita, Carlo Samori, Andrea Bonfanti
2023	J	`jnl`	A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. IEEE J. Solid State Circuits Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2023	—	`conf`	A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. ISSCC Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2023	—	`conf`	A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. ISSCC Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2023	—	`conf`	A Compact Wide-Input-Range Time-Domain Buck Converter with Fast Transient Response for Industrial Applications. ESSCIRC Paolo Melillo, Mauro Leoncini, Simone Zaffin, Alberto Brunero, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
2023	J	`jnl`	A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. IEEE J. Solid State Circuits Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2023	J	`jnl`	A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. IEEE J. Solid State Circuits Francesco Tesolin, Simone Mattia Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2023	J	`jnl`	Integration of loop gain measurement circuit for stability evaluation in DC/DC converters with time-based control. Integr. Mauro Leoncini, Alessandro Bertolini, Paolo Melillo, Salvatore Levantino, Massimo Ghioni
2023	J	`jnl`	Phase Noise Analysis of Periodically ON/OFF Switched Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Giacomo Castoro, Simone Mattia Dartizio, Andrea L. Lacaita, Salvatore Levantino
2023	—	`conf`	Time-Based Buck Converter with Variable Frequency DCM and ON-Time Correction for Seamless Transitions. PRIME Paolo Melillo, Simone Zaffin, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
2022	—	`conf`	A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters. NEWCAS Lorenzo Scaletti, Gabriele Bè, Angelo Parisi, Luca Bertulessi, Luca Ricci, Mario Mercandelli, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
2022	J	`jnl`	A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter. IEEE J. Solid State Circuits Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
2022	J	`jnl`	A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. IEEE J. Solid State Circuits Simone Mattia Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
2022	—	`conf`	A 68.6fs ISSCC Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
2022	J	`jnl`	A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations. IEEE Trans. Circuits Syst. II Express Briefs Gabriele Bè, Angelo Parisi, Luca Bertulessi, Luca Ricci, Lorenzo Scaletti, Mario Mercandelli, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
2022	—	`conf`	A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. CICC Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2022	J	`jnl`	A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. IEEE J. Solid State Circuits Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2022	—	`conf`	A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation. PRIME Alessandro Dago, Mauro Leoncini, Alberto Cattani, Salvatore Levantino, Massimo Ghioni
2022	—	`conf`	A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters. PRIME Paolo Melillo, Alessandro Dago, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
2022	J	`jnl`	Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology. IEEE J. Solid State Circuits Alessandro Garghetti, Andrea L. Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
2022	C	`conf`	Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs. ISCAS Luca Ricci, Lorenzo Scaletti, Gabriele Bè, Luca Bertulessi, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
2022	C	`conf`	Frequency Synthesizers for 5G Applications. VLSI-SoC Salvatore Levantino
2022	—	`conf`	Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control. PRIME Mauro Leoncini, Paolo Melillo, Alessandro Bertolini, Salvatore Levantino, Massimo Ghioni
2022	J	`jnl`	Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise. IEEE Trans. Circuits Syst. I Regul. Pap. Luca Bertulessi, Dmytro Cherniak, Mario Mercandelli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2022	—	`conf`	Recent Advances in High-Performance Frequency Synthesizer Design. CICC Salvatore Levantino
2022	J	`jnl`	Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Rabia Tugce Yazicigil, Salvatore Levantino
2021	—	`conf`	32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. ISSCC Alessio Santiccioli, Mario Mercandelli, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
2021	—	`conf`	A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. ISSCC Mario Mercandelli, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata, Francesco Tesolin, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea Leonardo Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
2021	—	`conf`	A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS. CICC Alessandro Garghetti, Andrea Leonardo Lacaita, David Seebacher, Matteo Bassi, Salvatore Levantino
2021	—	`conf`	A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter. A-SSCC Mario Mercandelli, Luca Bertulessi, Carlo Samori, Salvatore Levantino
2021	J	`jnl`	A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. Luca Avallone, Mario Mercandelli, Alessio Santiccioli, Michael Peter Kennedy, Salvatore Levantino, Carlo Samori
2021	J	`jnl`	A Novel Topology of Coupled Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Saleh Karman, Francesco Tesolin, Salvatore Levantino, Carlo Samori
2021	—	`conf`	An 800-mA Time-Based Boost Converter in 0.18µm BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency. ESSCIRC Mauro Leoncini, Alessandro Bertolini, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
2021	—	`conf`	Session 20 Overview: High-Performance VCOs Rf Subcommittee. ISSCC Andrea Bevilacqua, Salvatore Levantino, Hua Wang
2020	—	`conf`	17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking. ISSCC Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi, Dmytro Cherniak, Andrea Leonardo Lacaita, Carlo Samori, Salvatore Levantino
2020	—	`conf`	17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter. ISSCC Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea Leonardo Lacaita, Carlo Samori, Salvatore Levantino
2020	J	`jnl`	A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking. IEEE J. Solid State Circuits Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
2020	C	`conf`	A Novel Start-Up Technique for Time-Based Boost Converters with Seamless PFM/PWM Transition. ISCAS Tommaso Rosa, Mauro Leoncini, Salvatore Levantino, Massimo Ghioni
2020	J	`jnl`	Jitter Minimization in Digital PLLs with Mid-Rise TDCs. IEEE Trans. Circuits Syst. I Regul. Pap. Luca Avallone, Michael Peter Kennedy, Saleh Karman, Carlo Samori, Salvatore Levantino
2019	J	`jnl`	A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power. IEEE J. Solid State Circuits Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
2019	—	`conf`	A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. CICC Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
2019	J	`jnl`	A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS. IEEE J. Solid State Circuits Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2019	—	`conf`	A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS. ISSCC Luigi Grimaldi, Luca Bertulessi, Saleh Karman, Dmytro Cherniak, Alessandro Garghetti, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2019	J	`jnl`	A Novel Single-Inductor Injection-Locked Frequency Divider by Three With Dual-Injection Secondary Locking. IEEE Trans. Circuits Syst. I Regul. Pap. Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
2019	—	`conf`	Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper). CICC Dmytro Cherniak, Carlo Samori, Salvatore Levantino
2019	J	`jnl`	Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Alessio Santiccioli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2018	J	`jnl`	A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation. IEEE J. Solid State Circuits Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Roberto Nonis, Carlo Samori, Salvatore Levantino
2018	—	`conf`	A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. ISSCC Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Roberto Nonis, Salvatore Levantino
2018	J	`jnl`	A Background Calibration Technique to Control the Bandwidth of Digital PLLs. IEEE J. Solid State Circuits Mario Mercandelli, Luigi Grimaldi, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2018	C	`conf`	A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique. ISCAS Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
2018	C	`conf`	A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs. ISCAS Tuan Minh Vo, Carlo Samori, Salvatore Levantino
2018	—	`conf`	A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-Injection. ICECS Alessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino
2018	—	`conf`	A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range. ISSCC Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Salvatore Levantino
2018	C	`conf`	Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators. ISCAS Dmytro Cherniak, Luigi Grimaldi, Carlo Samori, Salvatore Levantino
2018	—	`conf`	Digital phase-locked loops. CICC Salvatore Levantino
2018	J	`jnl`	Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Mauro Leoncini, Andrea Bonfanti, Salvatore Levantino, Andrea L. Lacaita
2018	C	`conf`	Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers. ISCAS Alessandro Truppi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino, Marco Ronchi, Marco Sosio
2018	J	`jnl`	PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. IEEE Trans. Circuits Syst. I Regul. Pap. Dmytro Cherniak, Carlo Samori, Roberto Nonis, Salvatore Levantino
2018	J	`jnl`	Variation-Aware Modeling of Integrated Capacitors Based on Floating Random Walk Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paolo Maffezzoni, Zheng Zhang, Salvatore Levantino, Luca Daniel
2017	C	`conf`	A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL. ISCAS Tuan Minh Vo, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2017	C	`conf`	Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars. ISCAS Dmytro Chemiak, Salvatore Levantino, Carlo Samori, Roberto Nonis
2016	—	`conf`	Bang-bang digital PLLs. ESSCIRC Salvatore Levantino
2016	J	`jnl`	Introduction to the Special Section on the 2015 Radio Frequency Integrated Circuits Symposium. IEEE J. Solid State Circuits Salvatore Levantino
2015	J	`jnl`	A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop. IEEE J. Solid State Circuits Salvatore Levantino, Giovanni Marucci, Giovanni Marzin, Andrea Fenaroli, Carlo Samori, Andrea L. Lacaita
2014	—	`conf`	2.9 A Background calibration technique to control bandwidth in digital PLLs. ISSCC Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2014	—	`conf`	21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC. ISSCC Giovanni Marucci, Andrea Fenaroli, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2014	J	`jnl`	An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs. IEEE J. Solid State Circuits Salvatore Levantino, Giovanni Marzin, Carlo Samori
2014	J	`jnl`	Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
2014	J	`jnl`	Phase Noise of Pulse Injection-Locked Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Paolo Maffezzoni, Salvatore Levantino
2013	J	`jnl`	A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration. IEEE J. Solid State Circuits Salvatore Levantino, Giovanni Marzin, Carlo Samori, Andrea L. Lacaita
2013	C	`conf`	A spur cancellation technique for MDLL-based frequency synthesizers. ISCAS Giovanni Marzin, Andrea Fenaroli, Giovanni Marucci, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2013	—	`conf`	Advanced digital phase-locked loops. CICC Salvatore Levantino
2013	C	`conf`	An efficient method to compute phase-noise in injection-locked frequency dividers. ISCAS Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
2013	C	`conf`	Background adaptive linearization of high-speed digital-to-analog Converters. ISCAS Andrea Fenaroli, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2013	J	`jnl`	Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs. IEEE Trans. Circuits Syst. II Express Briefs Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
2013	C	`conf`	Minimum-jitter design of bang-bang PLLs in the presence of 1/f ISCAS Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
2013	—	`conf`	Nonlinearity cancellation in digital PLLs (Invited paper). CICC Salvatore Levantino, Carlo Samori
2013	C	`conf`	Simulating phase noise induced from cyclostationary noise sources. ISCAS Federico Pepe, Andrea Bonfanti, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori, Andrea L. Lacaita
2013	J	`jnl`	Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band. IEEE J. Solid State Circuits Federico Pepe, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2012	J	`jnl`	A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power. IEEE J. Solid State Circuits Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2012	—	`conf`	A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power. ISSCC Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2012	J	`jnl`	Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. Paolo Maffezzoni, Salvatore Levantino
2012	J	`jnl`	Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Salvatore Levantino, Paolo Maffezzoni
2012	J	`jnl`	Efficient Calculation of the Impulse Sensitivity Function in Oscillators. IEEE Trans. Circuits Syst. II Express Briefs Salvatore Levantino, Paolo Maffezzoni, Federico Pepe, Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita
2012	J	`jnl`	Phase-Noise Analysis and Simulation of LC Oscillator-Based Injection-Locked Frequency Dividers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Paolo Maffezzoni, Salvatore Levantino
2011	J	`jnl`	A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs IEEE J. Solid State Circuits Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2011	—	`conf`	A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. ISSCC Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2011	J	`jnl`	A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation. IEEE J. Solid State Circuits Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2011	—	`conf`	Behavioral phase-noise analysis of charge-pump phase-locked loops. ECCTD Paolo Maffezzoni, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita, Dario D'Amore, Mauro Santomauro
2011	J	`jnl`	Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL. IEEE Trans. Circuits Syst. II Express Briefs Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2011	C	`conf`	Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs. ISCAS Carlo Samori, Marco Zanuso, Salvatore Levantino, Andrea L. Lacaita
2010	—	`conf`	A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. ISSCC Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2010	J	`jnl`	AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic. EURASIP J. Embed. Syst. Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita
2010	J	`jnl`	Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division. IEEE Trans. Circuits Syst. II Express Briefs Salvatore Levantino, Luca Collamati, Carlo Samori, Andrea L. Lacaita
2010	—	`conf`	Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. ISSCC Salvatore Levantino, Marco Zanuso, Carlo Samori, Andrea L. Lacaita
2010	J	`jnl`	Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL. IEEE Trans. Circuits Syst. I Regul. Pap. Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2010	—	`conf`	Time-to-digital converter with 3-ps resolution and digital linearization algorithm. ESSCIRC Marco Zanuso, Salvatore Levantino, Alberto Puggelli, Carlo Samori, Andrea L. Lacaita
2009	—	`conf`	A glitch-corrector circuit for low-spur ADPLLs. ICECS Marco Zanuso, Salvatore Levantino, Davide Tasca, Daniele Raiteri, Carlo Samori, Andrea L. Lacaita
2009	—	`conf`	An all-digital architecture for low-jitter regulated delay lines. ICECS Salvatore Levantino, Marco Zanuso, Davide Tasca, Carlo Samori, Andrea L. Lacaita
2009	J	`jnl`	Noise Analysis and Minimization in Bang-Bang Digital PLLs. IEEE Trans. Circuits Syst. II Express Briefs Marco Zanuso, Davide Tasca, Salvatore Levantino, Andrea Donadel, Carlo Samori, Andrea L. Lacaita
2008	J	`jnl`	Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter. IEEE J. Solid State Circuits Luigi Panseri, Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2007	J	`jnl`	Quantization Effects in All-Digital Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs Paolo Madoglio, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2006	J	`jnl`	5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS. IEEE J. Solid State Circuits Luca Romanò, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2006	J	`jnl`	A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs. IEEE Trans. Circuits Syst. I Regul. Pap. Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2006	—	`conf`	Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter. CICC Luigi Panseri, Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2006	J	`jnl`	Multiphase LC oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Luca Romanò, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2004	J	`jnl`	A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider. IEEE J. Solid State Circuits Stefano Pellerano, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2004	—	`conf`	A multi-tank LC-oscillator [microwave oscillator example]. ICECS Luca Romanò, Carlo Samori, Salvatore Levantino, Andrea Bonfanti, Andrea L. Lacaita
2004	—	`conf`	Differential tuning oscillators with reduced flicker noise upconversion. ICECS Salvatore Levantino, Andrea Bonfanti, Luca Romanò, Carlo Samori, Andrea L. Lacaita
2004	—	`conf`	Fast-switching analog PLL with finite-impulse response. ISCAS (4) Salvatore Levantino, Luca Romanò, Carlo Samori, Andrea L. Lacaita
2004	J	`jnl`	Fast-switching analog PLL with finite-impulse response. IEEE Trans. Circuits Syst. I Regul. Pap. Salvatore Levantino, Marco Milani, Carlo Samori, Andrea L. Lacaita
2004	—	`conf`	Phase noise and accuracy in quadrature oscillators. ISCAS (1) Luca Romanò, Salvatore Levantino, Andrea Bonfanti, Carlo Samori, Andrea L. Lacaita
2004	J	`jnl`	Phase noise in digital frequency dividers. IEEE J. Solid State Circuits Salvatore Levantino, Luca Romanò, Stefano Pellerano, Carlo Samori, Andrea L. Lacaita
2003	J	`jnl`	A CMOS GSM IF-sampling circuit with reduced in-channel aliasing. IEEE J. Solid State Circuits Salvatore Levantino, Carlo Samori, Mihai Banu, Jack P. F. Glas, Vito Boccuzzi
2003	J	`jnl`	A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling. IEEE J. Solid State Circuits Sander L. J. Gierkink, Salvatore Levantino, Robert C. Frye, Carlo Samori, Vito Boccuzzi
2003	—	`conf`	A voltage-controlled oscillator for IEEE 802.11a and HiperLAN2 application. ESSCIRC Andrea Giovanni Bonfanti, Salvatore Levantino, Stefano Pellerano, Carlo Samori, Andrea L. Lacaita, Felice Torrisi
2002	J	`jnl`	Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. IEEE J. Solid State Circuits Salvatore Levantino, Carlo Samori, Andrea Bonfanti, Sander L. J. Gierkink, Andrea L. Lacaita, Vito Boccuzzi
2002	J	`jnl`	Integrated LC oscillators for frequency synthesis in wireless applications. IEEE Commun. Mag. Carlo Samori, Salvatore Levantino, Andrea L. Lacaita
2001	—	`conf`	A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications. CICC Carlo Samori, Salvatore Levantino, Vito Boccuzzi
2001	J	`jnl`	A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop. IEEE J. Solid State Circuits Alfio Zanchi, Carlo Samori, Salvatore Levantino, Andrea L. Lacaita
2001	—	`conf`	Automatic amplitude control loop for a 2-V, 2.5-GHz LC-tank VCO. CICC Alfio Zanchi, Andrea Bonfanti, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2000	C	`conf`	Fast simulation techniques for phase noise analysis of oscillators. ISCAS Salvatore Levantino, Alfio Zanchi, Andrea Bonfanti, Carlo Samori
2000	J	`jnl`	Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's. IEEE J. Solid State Circuits Carlo Samori, Andrea L. Lacaita, Alfio Zanchi, Salvatore Levantino, Giovanni Calí