Salvador Mir - RankMe

146 papers A* 1A 21B 16C 17Misc 14Journal 33Unranked 42

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	28 nm FD-SOI 4 K RF LNA Design Using DC Transistor Characterization Measurements. LATS Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mickael Casse, Philippe Galy
2025	—	`conf`	A Wideband Model for a Stacked Millimeter-Wave Transformer-based Power Combiner. PRIME Oumayma Belkhadra, Florent Cilici, Salvador Mir, Manuel J. Barragán, Gilles Montoriol, Emmanuel Pistono, Sylvain Bourdel
2025	—	`conf`	Multi-Agent Reinforcement Learning for Performance Calibration and Optimization of Integrated mmW Power Amplifiers. ATS Valentin Coppola, Florent Cilici, Sylvain Bourdel, Estelle Lauga-Larroze, Salvador Mir, Florence Podevin, Manuel J. Barragán
2024	—	`conf`	An Integrated Miniaturized VNA for On-Chip PA Mismatch Measurement. NewCAS Oumayma Belkhadra, Gilles Montoriol, Emmanuel Pistone, Hugo Vallee, Florent Cilici, Manuel J. Barragán, Salvador Mir, Sylvain Bourdel
2024	—	`conf`	LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching. NewCAS Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikaël Cassé, Philippe Galy
2023	C	`conf`	A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell. ISCAS Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán
2023	—	`conf`	A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA. NEWCAS Ankush Mamgain, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Jai Narayan Tripathi
2023	C	`conf`	Noise modeling using look-up tables and DC measurements for cryogenic applications. VLSI-SoC Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mikaël Cassé, Philippe Galy
2023	—	`conf`	Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation. LATS Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán
2023	—	`conf`	Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. LATS Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán
2022	C	`conf`	A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. VLSI-SoC Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán
2022	Misc	`conf`	Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
2022	—	`conf`	On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators. ATS Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán
2022	B	`conf`	Special Session on RF/5G Test. ETS William R. Eisenstadt, Mark Roos, Devin Morris, José Luis González-Jiménez, Christopery Mounet, Manuel J. Barragán, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Salvador Mir, Sylvain Bourdel, Marc Margalef-Rovira, Issa Alaji, Haitham Ghanem, Guillaume Ducournau, Christophe Gaquière
2021	B	`conf`	Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. ETS Ankush Mamgain, Manuel J. Barragán, Salvador Mir
2020	C	`conf`	A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
2020	J	`jnl`	Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahcène Bounceur, Salvador Mir, Reinhardt Euler, Kamel Beznia
2020	B	`conf`	On-chip reduced-code static linearity test of V ETS Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir
2020	—	`conf`	Static linearity BIST for V NEWCAS Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir
2019	B	`conf`	A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. ETS Hani Malloug, Manuel J. Barragán, Salvador Mir
2019	—	`conf`	Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits. SMACD Florent Cilici, Gildas Léger, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel
2019	J	`jnl`	Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. IEEE Trans. Very Large Scale Integr. Syst. Guillaume Renaud, Mamadou Diallo, Manuel J. Barragán, Salvador Mir
2019	A	`conf`	On the use of causal feature selection in the context of machine-learning indirect test. DATE Manuel J. Barragán, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Sylvain Bourdel, Salvador Mir
2019	C	`conf`	Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. VLSI-SoC Renato S. Feitoza, Manuel J. Barragán, Salvador Mir
2019	C	`conf`	Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. ISCAS Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel, Gildas Léger
2018	B	`conf`	Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. ETS Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel
2018	J	`jnl`	Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. J. Electron. Test. Hani Malloug, Manuel J. Barragán, Salvador Mir
2018	C	`conf`	Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. IOLTS Renato S. Feitoza, Manuel J. Barragán, Salvador Mir, Daniel Dzahini
2017	Misc	`conf`	Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. VTS Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragán, Salvador Mir
2017	B	`conf`	Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. ETS Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Hervé Le Gall
2017	B	`conf`	Mixed-signal BIST computation offloading using IEEE 1687. ETS Michele Portolan, Manuel J. Barragán, Rshdee Alhakim, Salvador Mir
2016	J	`jnl`	A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet
2016	J	`jnl`	A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Manuel J. Barragán, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2016	—	`conf`	ADC Techniques for Optimized Conversion Time in CMOS Image Sensors. IMSE Cédric Pastorelli, Pascal Mellot, Salvador Mir, Cédric Tubert
2016	A	`conf`	Built-in test of millimeter-Wave circuits based on non-intrusive sensors. DATE Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld
2016	B	`conf`	Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragán, Salvador Mir
2016	J	`jnl`	Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. IEEE Des. Test Manuel J. Barragán, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2015	J	`jnl`	A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters. ACM Trans. Design Autom. Electr. Syst. Kamel Beznia, Ahcène Bounceur, Reinhardt Euler, Salvador Mir
2015	A	`conf`	Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. ITC Haralampos-G. D. Stratigopoulos, Manuel J. Barragán, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2015	J	`jnl`	Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. IEEE Trans. Circuits Syst. I Regul. Pap. Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet
2015	B	`conf`	High frequency jitter estimator for SoCs. ETS Hervé Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu
2015	Misc	`conf`	Horizontal-FPN fault coverage improvement in production test of CMOS imagers. VTS Richun Fei, Jocelyn Moreau, Salvador Mir, Alexis Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou
2015	J	`jnl`	Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors. J. Electron. Test. Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld
2015	—	`conf`	Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors. ISVLSI Athanasios Dimakos, Martin Andraud, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, Salvador Mir
2014	C	`conf`	Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. VLSI-SoC Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán
2014	—	`conf`	Low-cost EVM built-in test of RF transceivers. IDT Ayssar Serhan, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
2014	—	`conf`	On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. ATS Guillaume Renaud, Manuel J. Barragán, Salvador Mir, Marc Sabut
2014	—	`conf`	Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes. MWSCAS Josep Altet, Eduardo Aldrete-Vidrio, Ferran Reverter, Didac Gómez, José Luis González, Marvin Onabajo, José Silva-Martínez, B. Martineau, X. Perpiñà, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Xavier Aragonès, Xavier Jordà, Miquel Vellvehí, Stefan Dilhaire, Salvador Mir, Diego Mateo
2014	C	`conf`	Solutions for the self-adaptation of communicating systems in operation. IOLTS Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos
2014	—	`conf`	Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST. VLSI-SoC (Selected Papers) Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán
2013	—	`conf`	BIST of interconnection lines in the pixel matrix of CMOS imagers. IWASI Richun Fei, Jocelyn Moreau, Salvador Mir
2013	Misc	`conf`	Defect-oriented non-intrusive RF test using on-chip temperature sensors. VTS Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet
2013	B	`conf`	Efficient minimization of test frequencies for linear analog circuits. ETS Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir
2013	A	`conf`	Fault modeling and diagnosis for nanometric analog circuits. ITC Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
2013	—	`conf`	Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods. VLSI-SoC (Selected Papers) Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Salvador Mir, Yann Kieffer
2013	—	`conf`	Multivariate statistical techniques for analog parametric test metrics estimation. DTIS Ke Huang, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Salvador Mir, Ahcène Bounceur
2013	C	`conf`	New techniques for selecting test frequencies for linear analog circuits. VLSI-SoC Mohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir
2013	Misc	`conf`	Reduced code linearity testing of pipeline adcs in the presence of noise. VTS Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret
2013	J	`jnl`	Reduced-Code Linearity Testing of Pipeline ADCs. IEEE Des. Test Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Gerard Bret
2013	—	`conf`	Statistical modelling of analog circuits for test metrics computation. DTIS Kamel Beznia, Ahcène Bounceur, Salvador Mir, Reinhardt Euler
2013	A	`conf`	True non-intrusive sensors for RF built-in test. ITC Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
2012	—	`conf`	Accurate estimation of analog test metrics with extreme circuits. ICECS Kamel Beznia, Ahcène Bounceur, Louay Abdallah, Ke Huang, Salvador Mir, Reinhardt Euler
2012	J	`jnl`	Adaptive Alternate Analog Test. IEEE Des. Test Comput. Haralampos-G. D. Stratigopoulos, Salvador Mir
2012	Misc	`conf`	Analog/RF test ordering in the early stages of production testing. VTS Nourredine Akkouche, Salvador Mir, Emmanuel Simeu, Mustapha Slamani
2012	J	`jnl`	Diagnosis of Local Spot Defects in Analog Circuits. IEEE Trans. Instrum. Meas. Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir, Camelia Hora, Yizi Xing, Bram Kruseman
2012	B	`conf`	Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. ETS Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Naudet, Christophe Forel
2012	A	`conf`	Experiences with non-intrusive sensors for RF built-in test. ITC Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma
2012	A	`conf`	Testing RF circuits with true non-intrusive built-in sensors. DATE Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet
2012	—	`ed.`	VLSI-SoC: Advanced Research for Systems on Chip - 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers VLSI-SoC (Selected Papers) Salvador Mir, Chi-Ying Tsui, Ricardo Reis, Oliver C. S. Choy
2011	J	`jnl`	Estimation of Analog Parametric Test Metrics Using Copulas. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahcène Bounceur, Salvador Mir, Haralampos-G. D. Stratigopoulos
2011	—	`conf`	Implicit test of high-speed analog circuits using non-intrusive sensors. ECCTD Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
2011	—	`conf`	On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study. Asian Test Symposium Alexios Spyronasios, Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir
2011	J	`jnl`	RF Front-End Test Using Built-in Sensors. IEEE Des. Test Comput. Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma
2010	—	`conf`	Adaptive Logical Control of RF LNA Performances for Efficient Energy Consumption. VLSI-SoC (Selected Papers) Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni
2010	C	`conf`	Adaptive logical control of RF LNA performances for efficient energy consumption. VLSI-SoC Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni
2010	A	`conf`	Analog test metrics estimates with PPM accuracy. ICCAD Haralampos-G. D. Stratigopoulos, Salvador Mir
2010	—	`conf`	Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation. Asian Test Symposium Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
2010	B	`conf`	Defect filter for alternate RF test. ETS Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev
2010	Misc	`conf`	Density estimation for analog/RF test problem solving. VTS Salvador Mir, Haralampos-G. D. Stratigopoulos, Ahcène Bounceur
2010	J	`jnl`	Design of a SAW-based chemical sensor with its microelectronics front-end interface. Microelectron. J. Fabio Cenni, Jeremie Cazalbou, Salvador Mir, Libor Rufer
2010	A	`conf`	Fault diagnosis of analog circuits based on machine learning. DATE Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir
2010	—	`conf`	Low Frequency Test for RF MEMS Switches. DELTA Gustavo Pamplona Rehder, Salvador Mir, Libor Rufer, Emmanuel Simeu, Hoang Nam Nguyen
2010	Misc	`conf`	Ordering of analog specification tests based on parametric defect level estimation. VTS Nourredine Akkouche, Salvador Mir, Emmanuel Simeu
2010	B	`conf`	Sensors for built-in alternate RF test. ETS Louay Abdallah, Haralampos-G. D. Stratigopoulos, Christophe Kelma, Salvador Mir
2009	B	`conf`	Defect Filter for Alternate RF Test. ETS Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev
2009	A	`conf`	Enrichment of limited training sets in machine-learning-based analog/RF test. DATE Haralampos-G. D. Stratigopoulos, Salvador Mir, Yiorgos Makris
2009	J	`jnl`	Evaluation of Analog/RF Test Measurements at the Design Stage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haralampos-G. D. Stratigopoulos, Salvador Mir, Ahcène Bounceur
2009	Misc	`conf`	Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors. VTS Livier Lizarraga, Salvador Mir, Gilles Sicard
2009	C	`conf`	Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study. ICCD Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir
2009	—	`conf`	Parameter identification of RF transceiver blocks using regressive models. PDeS Rafik Khereddine, Emmanuel Simeu, Salvador Mir
2009	J	`jnl`	Pseudorandom BIST for test and characterization of linear and nonlinear MEMS. Microelectron. J. Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur, Emmanuel Simeu
2008	A	`conf`	A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation. DATE Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir
2008	J	`jnl`	Using Signal Envelope Detection for Online and Offline RF MEMS Switch Testing. VLSI Design Emmanuel Simeu, Hoang Nam Nguyen, Philippe Cauvet, Salvador Mir, Libor Rufer, Rafik Khereddine
2007	A	`conf`	A stereo audio Σ∑ ADC architecture with embedded SNDR self-test. ITC Luís Rolíndez, Salvador Mir, Jean-Louis Carbonéro, Dimitri Goguet, Nabil Chouba
2007	C	`conf`	Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches. IOLTS Emmanuel Simeu, Salvador Mir, R. Kherreddine, Hoang Nam Nguyen
2007	J	`jnl`	Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing. J. Electron. Test. Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez
2007	—	`conf`	Evaluation of a BIST Technique for CMOS Imagers. ATS Livier Lizarraga, Salvador Mir, Gilles Sicard
2007	A	`conf`	Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model. DATE Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro
2007	—	`conf`	Test Education in the Global Economy. ATS Jacob Abraham, Salvador Mir, Yinghua Min, Jeremy Wang, Cheng-Wen Wu
2007	—	`ed.`	VLSI-SoC: Research Trends in VLSI and Systems on Chip - Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2006), October 16-18, 2006, Nice, France VLSI-SoC (Selected Papers) Giovanni De Micheli, Salvador Mir, Ricardo Reis
2006	J	`jnl`	A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting. J. Electron. Test. Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro
2006	Misc	`conf`	A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters. VTS Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro
2006	J	`jnl`	Built-in-self-test techniques for MEMS. Microelectron. J. Salvador Mir, Libor Rufer, Achraf Dhayni
2006	—	`conf`	CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization. VLSI-SoC (Selected Papers) Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu
2006	C	`conf`	CAT platform for analogue and mixed-signal test evaluation and optimization. VLSI-SoC Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu
2006	J	`jnl`	Guest Editorial. J. Electron. Test. Salvador Mir, Kwang-Ting (Tim) Cheng, Andrew Richardson
2006	A	`conf`	Pseudorandom functional BIST for linear and nonlinear MEMS. DATE Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur
2006	C	`conf`	Study of a BIST Technique for CMOS Active Pixel Sensors. VLSI-SoC Livier Lizarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur
2005	—	`conf`	A built-in I ESSCIRC Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir
2005	J	`jnl`	A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation. Microelectron. J. Guillaume Prenat, Salvador Mir, Diego Vázquez, Luís Rolíndez
2005	J	`jnl`	Analog and mixed signal test techniques for SOC development. Microelectron. J. Bozena Kaminska, Stephen K. Sunter, Salvador Mir
2005	B	`conf`	Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities. ETS Achraf Dhayni, Salvador Mir, Libor Rufer
2005	J	`jnl`	On-Chip Pseudorandom MEMS Testing. J. Electron. Test. Libor Rufer, Salvador Mir, Emmanuel Simeu, C. Domingues
2005	C	`conf`	On-chip Pseudorandom Testing for Linear and Nonlinear MEMS. VLSI-SoC Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur
2005	A	`conf`	Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach. DATE Rabeb Kheriji, V. Danelon, Jean-Louis Carbonéro, Salvador Mir
2004	A	`conf`	A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns. DATE Luís Rolíndez, Salvador Mir, Guillaume Prenat, Ahcène Bounceur
2004	B	`conf`	Mems built-in-self-test using MLS. ETS Achraf Dhayni, Salvador Mir, Libor Rufer
2004	—	`conf`	On-chip testing of embedded silicon transducers. SoCC Salvador Mir, Benoît Charlot, Libor Rufer, Bernard Courtois
2004	Misc	`conf`	On-chip testing of embedded transducers. VLSI Design Salvador Mir, Libor Rufer, Bernard Courtois
2003	—	`conf`	An implementation of memory-based on-chip analogue test signal generation. ASP-DAC Salvador Mir, Luís Rolíndez, Christian Domigues, Libor Rufer
2003	J	`jnl`	Building an analogue fault simulation tool and its application to MEMS. Microelectron. J. Cosmin Roman, Salvador Mir, Benoît Charlot
2003	C	`conf`	On-Line Testable Decimation Filter Design for AMS Systems. IOLTS Mohammad A. Naal, Emmanuel Simeu, Salvador Mir
2002	Misc	`conf`	SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? VTS Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim
2001	—	`conf`	An Analog-based Approach for MEMS Testing. LATW Bernard Courtois, Salvador Mir, Benoît Charlot, Marcelo Lubaszewski
2001	Misc	`conf`	Electrically Induced Stimuli For MEMS Self-Test. VTS Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois
2001	J	`jnl`	Generation of Electrically Induced Stimuli for MEMS Self-Test. J. Electron. Test. Benoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois
2000	J	`jnl`	Design of self-checking fully differential circuits and boards. IEEE Trans. Very Large Scale Integr. Syst. Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois
2000	J	`jnl`	Extending Fault-Based Testing to Microelectromechanical Systems. J. Electron. Test. Salvador Mir, Benoît Charlot, Bernard Courtois
2000	—	`conf`	Towards design and validation of mixed-technology SOCs. ACM Great Lakes Symposium on VLSI Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz
1999	Misc	`conf`	Design and Test of MEMs. VLSI Design Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimír Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner
1999	—	`conf`	Extending fault-based testing to microelectromechanical systems. ETW Salvador Mir, Benoît Charlot, Bernard Courtois
1999	A	`conf`	Fault modeling of suspended thermal MEMS. ITC Benoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois
1999	J	`jnl`	On the Integration of Design and Test for Chips Embedding MEMS. IEEE Des. Test Comput. Salvador Mir, Benoît Charlot
1998	—	`conf`	A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. SBCCI Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand
1998	A	`conf`	Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems. ITC A. Castillejo, D. Veychard, Salvador Mir, Jean-Michel Karam, Bernard Courtois
1998	A	`conf`	Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. DATE Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas
1997	A*	`conf`	SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. DAC Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas
1996	A	`conf`	ABILBO: Analog BuILt-in Block Observer. ICCAD Marcelo Lubaszewski, Salvador Mir, Leandro Pulz
1996	—	`conf`	Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits. ED&TC Salvador Mir, Bernard Courtois, Marcelo Lubaszewski, Vladimir Kolarik
1996	—	`conf`	Design of high-performance band-pass sigma-delta modulator with concurrent error detection. ICECS Fabrizio Francesconi, Valentino Liberali, Marcelo Lubaszewski, Salvador Mir
1996	J	`jnl`	Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets. J. Electron. Test. Salvador Mir, Marcelo Lubaszewski, Bernard Courtois
1996	J	`jnl`	Unified built-in self-test for fully differential analog circuits. J. Electron. Test. Salvador Mir, Marcelo Lubaszewski, Bernard Courtois
1995	J	`jnl`	Analog checkers with absolute and relative tolerances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois
1995	—	`conf`	Mixed-signal circuits and boards for high safety applications. ED&TC Marcelo Lubaszewski, Vladimir Kolarik, Salvador Mir, C. Nielsen, Bernard Courtois
1994	A	`conf`	Built-in self-test and fault diagnosis of fully differential analogue circuits. ICCAD Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois
1994	—	`conf`	Re-engineering hardware specifications by exploiting design semantics. EURO-DAC Salvador Mir, Nick Filer