Salvador Manich

32 papers A 2B 2C 1Misc 2Journal 11Unranked 14
YearRankTypeTitle / Venue / Authors
2024 — conf
Engineering UGR-VCMTCF RRAM Model for Adjusting to TiN/Ti/HfO2/W Devices.
DCIS
Vahab Mahboubi, Á. Gómez, Antonio Calomarde, Daniel Arumí, R. Rodríguez, Salvador Manich
2024 C conf
On the Fine Tuning of RRAM Resistance Under Variability Using Current Pulses at SET.
IOLTS
Vahab Mahboubi, Á. Gómez, Antonio Calomarde, Daniel Arumí, R. Rodríguez, Salvador Manich
2023 J jnl
True Random Number Generator Based on the Variability of the High Resistance State of RRAMs.
IEEE Access
Maryam Akbari, Sattar Mirzakuchaki, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Francesca Campabadal, Mireia Bargallo González, Rosa Rodríguez-Montañés
2022 J jnl
Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact.
IEEE Access
Antonio Calomarde, Salvador Manich, Antonio Rubio, Francisco Gámiz
2022 — conf
On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data.
DCIS
Vahab Mahboubi, Daniel Arumí, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Salvador Manich
2021 — conf
Low Cost AES Protection Against DPA Using Rolling Codes.
DCIS
P. Albiol, Salvador Manich, Daniel Arumí, Rosa Rodríguez-Montañés, Álvaro Gómez-Pau
2021 — conf
Simulation of serial RRAM cell based on a Verilog-A compact model.
DCIS
Binbin Yang, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Juan Bautista Roldán, Mireia Bargallo González, Francesca Campabadal, Liang Fang
2019 J jnl
A Calibratable Detector for Invasive Attacks.
IEEE Trans. Very Large Scale Integr. Syst.
Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich
2018 J jnl
The Low Area Probing Detector as a Countermeasure Against Invasive Attacks.
IEEE Trans. Very Large Scale Integr. Syst.
Michael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl
2017 J jnl
Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis.
Microelectron. J.
Madalin Neagu, Salvador Manich
2016 — conf
RRAM based cell for hardware security applications.
IVSW
Daniel Arumí, Salvador Manich, Rosa Rodríguez-Montañés
2015 J jnl
Improving security in cache memory by power efficient scrambling technique.
IET Comput. Digit. Tech.
Madalin-Ioan Neagu, Liviu Miclea, Salvador Manich
2014 — conf
A Low Area Probing Detector for Power Efficient Security ICs.
RFIDSec
Michael Weiner, Salvador Manich, Georg Sigl
2014 B conf
Interleaved scrambling technique: A novel low-power security layer for cache memories.
ETS
Madalin Neagu, Liviu Miclea, Salvador Manich
2013 J jnl
A Highly Time Sensitive XOR Gate for Probe Attempt Detectors.
IEEE Trans. Circuits Syst. II Express Briefs
Salvador Manich, Martin Strasser
2013 A conf
Differential scan-path: A novel solution for secure design-for-testability.
ITC
Salvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl
2012 — conf
Detection of probing attempts in secure ICs.
HOST
Salvador Manich, Markus S. Wamser, Georg Sigl
2010 B conf
Design and implementation of Automatic Test Equipment IP module.
ETS
S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich
2007 J jnl
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Salvador Manich, Lucas Garcia-Deiros, Joan Figueras
2004 Misc conf
BIST Technique by Equally Spaced Test Vector Sequences.
VTS
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
2004 J jnl
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.
J. Electron. Test.
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
2003 — conf
On the selection of efficient arithmetic additive test pattern generators [logic test].
ETW
Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
2003 — conf
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.
PATMOS
Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodríguez-Sánchez
2002 — conf
On High-Quality, Low Energy BIST Preparation at RT-Level.
LATW
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
2002 A conf
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.
ITC
Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
2000 J jnl
Low Power BIST by Filtering Non-Detecting Vectors.
J. Electron. Test.
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
1999 — conf
Low power BIST by filtering non-detecting vectors.
ETW
Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
1999 — conf
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
ISCAS (1)
Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
1997 J jnl
Fault-Secure Parity Prediction Arithmetic Operators.
IEEE Des. Test Comput.
Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras
1997 — conf
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.
ED&TC
Salvador Manich, Joan Figueras
1996 — conf
Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations.
ED&TC
Michael Nicolaidis, Salvador Manich, Joan Figueras
1996 Misc conf
Enhancing realistic fault secureness in parity prediction array arithmetic operators by I
VTS
Salvador Manich, Michael Nicolaidis, Joan Figueras