Saleh Abdel-Hafeez

19 papers C 2Journal 14Unranked 3
YearRankTypeTitle / Venue / Authors
2024 J jnl
A fast and cost-effective integer restoring division hardware.
Comput. Electr. Eng.
Saleh Abdel-Hafeez
2023 J jnl
A novel self-timing CMOS first-edge take-all circuit for on-chip communication systems.
IET Comput. Digit. Tech.
Saleh Abdel-Hafeez, Shadi M. Harb
2023 J jnl
Programmable Feedback Shift Register.
Circuits Syst. Signal Process.
Saleh Abdel-Hafeez
2022 J jnl
Design of memory Alias Table based on the SRAM 8T-Cell.
Int. J. Circuit Theory Appl.
Saleh Abdel-Hafeez, Sanabel Otoom, Muhannad Quwaider
2021 J jnl
Reconfigurable FIFO memory circuit for synchronous and asynchronous communication.
Int. J. Circuit Theory Appl.
Saleh Abdel-Hafeez, Ann Gordon-Ross
2019 — conf
A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems.
ISVLSI
Ann Gordon-Ross, Saleh Abdel-Hafeez, Mohamad Hammam Alsafrjalani
2018 J jnl
A comparison-free sorting algorithm on CPUs and GPUs.
J. Supercomput.
Saleh Abdel-Hafeez, Ann Gordon-Ross, Samer Abubaker
2018 J jnl
High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder.
Circuits Syst. Signal Process.
Saleh Abdel-Hafeez, Ali M. Shatnawi
2017 J jnl
An Efficient O(N) Comparison-Free Sorting Algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Saleh Abdel-Hafeez, Ann Gordon-Ross
2013 J jnl
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree.
IEEE Trans. Very Large Scale Integr. Syst.
Saleh Abdel-Hafeez, Ann Gordon-Ross, Behrooz Parhami
2012 — conf
A double data rate 8T-cell SRAM architecture for systems-on-chip.
ISSoC
Saleh Abdel-Hafeez, Mohammad Shatnawi, Ann Gordon-Ross
2011 J jnl
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic.
IEEE Trans. Very Large Scale Integr. Syst.
Saleh Abdel-Hafeez, Ann Gordon-Ross
2011 J jnl
A Gigahertz Digital CMOS Divide-by-
Circuits Syst. Signal Process.
Saleh Abdel-Hafeez, Ann Gordon-Ross
2011 J jnl
A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter.
Informatica (Slovenia)
Saleh Abdel-Hafeez, Ann Gordon-Ross, Asem Albosul, Ahmad Shatnawi, Shadi M. Harb
2008 J jnl
CMOS Eight-Transistor Memory Cell for Low-Dynamic-Power High-Speed Embedded SRAM.
J. Circuits Syst. Comput.
Saleh Abdel-Hafeez, Anas S. Matalkah
2008 C conf
High speed digital CMOS divide-by-N fequency divider.
ISCAS
Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
2007 C conf
A low-power CAM using a 12-transistor design cell.
VLSI-SoC
Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
2007 — conf
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports.
PATMOS
Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
2006 J jnl
A VLSI High-Performance Priority Encoder Using Standard CMOS Library.
IEEE Trans. Circuits Syst. II Express Briefs
Saleh Abdel-Hafeez, Shadi M. Harb