Saket Gupta

16 papers A 1Journal 9Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
Optimal power flow solution using novel optimization technique: A case study.
Expert Syst. Appl.
Saket Gupta, Mohd Bilal, Mohd Zuhaib, Laxmi Srivastava, Hasmat Malik, Fausto Pedro García Márquez, Asyraf Afthanorhan
2025 J jnl
Optimal power flow solutions for normal and critical loading scenarios using hybrid Rao-2 sine cosine algorithm.
Comput. Electr. Eng.
Udit Mittal, Uma Nangia, Narender Kumar Jain, Saket Gupta
2024 J jnl
A Comprehensive Review on STATCOM: Paradigm of Modeling, Control, Stability, Optimal Location, Integration, Application, and Installation.
IEEE Access
Sandeep Sharma, Saket Gupta, Mohd Zuhaib, Vijay Bhuria, Hasmat Malik, AbdulAziz AlMutairi, Asyraf Afthanorhan, Mohammad Asef Hossaini
2024 J jnl
Optimal power flow solution using a learning-based sine-cosine algorithm.
J. Supercomput.
Udit Mittal, Uma Nangia, Narender Kumar Jain, Saket Gupta
2018 — conf
Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs.
IRPS
Balaji Narasimham, Saket Gupta, Daniel S. Reed, J. K. Wang, Nick Hendrickson, Hasan Taufique
2016 J jnl
Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories.
IEEE Trans. Circuits Syst. I Regul. Pap.
Saket Gupta, Carl Monzel, Daniel S. Reed, Yifei Zhang, Mark Winter, Myron Buer
2015 — conf
Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs.
IRPS
Balaji Narasimham, Jung K. Wang, Narayana Vedula, Saket Gupta, Brandon Bartz, Carl Monzel, Indranil Chatterjee, Bharat L. Bhuva, Ronald D. Schrimpf, Robert A. Reed
2014 J jnl
Variation-Aware Variable Latency Design.
IEEE Trans. Very Large Scale Integr. Syst.
Saket Gupta, Sachin S. Sapatnekar
2013 J jnl
BioinQA: metadata-based multi-document QA system for addressing the issues in biomedical domain.
Int. J. Data Min. Model. Manag.
Sparsh Mittal, Saket Gupta, Ankush Mittal
2013 J jnl
Employing circadian rhythms to enhance power and reliability.
ACM Trans. Design Autom. Electr. Syst.
Saket Gupta, Sachin S. Sapatnekar
2012 — conf
BTI-aware design using variable latency units.
ASP-DAC
Saket Gupta, Sachin S. Sapatnekar
2012 A conf
Circuit reliability: From Physics to Architectures: Embedded tutorial paper.
ICCAD
Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar
2012 J jnl
Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations.
IEEE Trans. Very Large Scale Integr. Syst.
Saket Gupta, Sachin S. Sapatnekar
2012 — conf
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation.
ASP-DAC
Saket Gupta, Sachin S. Sapatnekar
2012 — conf
Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors.
CICC
Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim
2010 — conf
Current source modeling in the presence of body bias.
ASP-DAC
Saket Gupta, Sachin S. Sapatnekar