Sajjad Parvin

19 papers A 2C 2Misc 2Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2026 Misc conf
DIVIAC: Library of Input Data Aware Approximate Dividers with Partial Exact Minimization.
VLSID
Chandan Kumar Jha, Sallar Ahmadi-Pour, Sajjad Parvin, Rolf Drechsler
2025 J jnl
Auto-OPS: A Framework for Automated Optical Probing Simulation on GDS-II.
IEEE Embed. Syst. Lett.
Paul Flammarion, Sajjad Parvin, Frank Sill Torres, Rolf Drechsler
2025 J jnl
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits.
ACM Trans. Design Autom. Electr. Syst.
Sallar Ahmadi-Pour, Sajjad Parvin, Chandan Kumar Jha, Rolf Drechsler
2025 J jnl
OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2025 Misc conf
True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET.
VLSID
Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
2024 A conf
Hidden Cost of Circuit Design with RFETs.
DATE
Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
2024 J jnl
Lower the RISC: Designing optical-probing-attack-resistant cores.
Microprocess. Microsystems
Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
2023 A conf
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing.
DATE
Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2023 — conf
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing.
ISVLSI
Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
2023 — conf
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core.
COINS
Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
2023 — conf
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study.
ASP-DAC
Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
2022 — conf
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques.
ASP-DAC
Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
2021 — conf
A Study on Hardware-Aware Training Techniques for Feedforward Artificial Neural Networks.
ISVLSI
Sajjad Parvin, Mustafa Altun
2021 — conf
Efficient Hardware Implementation of Convolution Layers Using Multiply-Accumulate Blocks.
ISVLSI
Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun
2021 J jnl
Efficient Hardware Realizations of Feedforward Artificial Neural Networks.
CoRR
Mohammadreza Esmali Nojehdeh, Sajjad Parvin, Mustafa Altun
2020 C conf
Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks.
ISCAS
Levent Aksoy, Sajjad Parvin, Mohammadreza Esmali Nojehdeh, Mustafa Altun
2019 C conf
Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates.
IOLTS
Sajjad Parvin, Mustafa Altun
2019 J jnl
Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates.
IEEE Access
Sajjad Parvin, Mustafa Altun
2018 J jnl
Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits.
IEEE Access
Mustafa Altun, Sajjad Parvin, M. Hüsrev Cilasun