Saiyu Ren

16 papers Journal 7Unranked 9
YearRankTypeTitle / Venue / Authors
2021 J jnl
A 170 MHz to 330 MHz Wideband 90 nm CMOS RC-CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver.
Circuits Syst. Signal Process.
Xiaomeng Zhang, Shuo Li, Ray Siferd, Saiyu Ren
2019 J jnl
Logistic Function Based Memristor Model With Circuit Application.
IEEE Access
Isaac Abraham, Saiyu Ren, Raymond E. Siferd
2019 J jnl
Low-Cost and High-Performance 8 × 8 Booth Multiplier.
Circuits Syst. Signal Process.
N. V. Vijaya Krishna Boppana, Jeevani Kommareddy, Saiyu Ren
2019 — conf
Memristor based multifunction oscillator.
MWSCAS
Isaac Abraham, Saiyu Ren
2018 J jnl
Hardware Trojan detection by timing measurement: Theory and implementation.
Microelectron. J.
Hao Xue, Saiyu Ren
2016 J jnl
A Low-Power and Area-Efficient 64-Bit Digital Comparator.
J. Circuits Syst. Comput.
N. V. Vijaya Krishna Boppana, Saiyu Ren
2016 J jnl
High Frequency Unity Gain Buffer in 90-nm CMOS Technology.
J. Circuits Syst. Comput.
Shuo Li, Xiaomeng Zhang, Saiyu Ren
2015 J jnl
A 1-6 GHz analog radio frequency power driver in 90 nm complementary metal-oxide semiconductor technology for wireless applications.
Int. J. Circuit Theory Appl.
Saiyu Ren, Isaac Abraham, Seng Hong
2015 — conf
A 1.1-8.2 GHz tuning range In-phase and Quadrature output DCO design in 90 nm CMOS technology.
MWSCAS
Eswar Raju Suraparaju, Pushpak Vasanth Rayudu Arja, Saiyu Ren
2015 — conf
FPGA design space exploration of IDEA cryptography IP core.
MWSCAS
Dinesh Varma Penumetcha, Jiafeng Xie, Saiyu Ren
2013 — conf
Design and implementation of a 16-bit flexible ROM-less direct digital synthesizer.
MWSCAS
Sunny Raj Dommaraju, Saiyu Ren, George Y. Lee
2013 — conf
Digital Down Converter optimization.
MWSCAS
Joe Gerhardt, Saiyu Ren
2013 — conf
Passive component stacking to aid power supply decoupling.
MWSCAS
Christopher Benedik, Saiyu Ren
2011 — conf
CMOS 1.6 GHz Bandwidth 12 Bit Time Interleaved Pipelined ADC.
ITNG
Saiyu Ren, Ray Siferd
2009 — conf
Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS.
SoCC
Saiyu Ren, Ray Siferd
2004 — conf
Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications.
SoCC
Saiyu Ren, Ray Siferd, Robert Blumgold