Sailesh K. Rao

14 papers A 1C 3Misc 1Journal 8Unranked 1
YearRankTypeTitle / Venue / Authors
1997 — conf
100BASE-T2: 100 Mbit/s Ethernet over Two Pairs of Category-3 Cabling.
ICC (2)
Giovanni Cherubini, John Creigh, Sedat Ölçer, Sailesh K. Rao, Gottfried Ungerboeck
1997 J jnl
100BASE-T2: a new standard for 100 Mb/s Ethernet transmission over voice-grade cables.
IEEE Commun. Mag.
Giovanni Cherubini, Sedat Ölçer, Gottfried Ungerboeck, John Creigh, Sailesh K. Rao
1995 J jnl
The ATM physical layer.
Comput. Commun. Rev.
Sailesh K. Rao, Mehdi Hatamian
1994 C conf
Application Specific Memories for ATM Packet Switching.
ISCAS
Alex G. Dickinson, Chris J. Nicol, Sailesh K. Rao, Mehdi Hatamian
1993 J jnl
A 200 MHz CMOS broad-band switching chip.
IEEE J. Solid State Circuits
Jay H. O'Neill, Bryan D. Ackland, Sailesh K. Rao, Mehdi Hatamian
1992 J jnl
The Rectilinear Steiner Arborescence Problem.
Algorithmica
Sailesh K. Rao, P. Sadayappan, Frank K. Hwang, Peter W. Shor
1990 C conf
A design environment for high performance VLSI signal processing.
ICCD
Sailesh K. Rao, Mehdi Hatamian, Bryan D. Ackland
1990 J jnl
On the Analysis of Synchronous Computing Systems.
SIAM J. Comput.
Juan-Manuel Jover, Thomas Kailath, Hanoch Lev-Ari, Sailesh K. Rao
1989 A conf
Communication reduction for distributed sparse matrix factorization on a processor mesh.
SC
Ponnuswamy Sadayappan, Sailesh K. Rao
1989 C conf
The matrix transform chip.
ICCD
Sailesh K. Rao
1988 J jnl
Regular iterative algorithms and their implementation on processor arrays.
Proc. IEEE
Sailesh K. Rao, Thomas Kailath
1987 J jnl
Array architectures for iterative algorithms.
Proc. IEEE
Hosagrahar Visvesvaraya Jagadish, Sailesh K. Rao, Thomas Kailath
1987 J jnl
Design of minimal-degree compensators with assignable poles or structure.
Autom.
Sailesh K. Rao, Chi-Tsong Chen
1984 Misc conf
Pipelined orthogonal digital lattice filters.
ICASSP
Sailesh K. Rao, Thomas Kailath