Said Belkouch - RankMe

18 papers C 2Misc 1Journal 9Unranked 6

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs. ICECOCS Noureddine Chabini, Said Belkouch, Mohamed Najoui
2022	J	`jnl`	Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures. Comput. Electr. Eng. Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou, Anas Hatim, Said Belkouch, Atman Jbari, Noureddine Chabini
2021	J	`jnl`	An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP. Microprocess. Microsystems Abdessamad Klilou, Assia Arsalane, Mohamed Najoui, Said Belkouch
2020	J	`jnl`	Efficient adaptive load balancing approach for compressive background subtraction algorithm on heterogeneous CPU-GPU platforms. J. Real Time Image Process. Lhoussein Mabrouk, Sylvain Huet, Dominique Houzet, Said Belkouch, Abdelkrim Hamzaoui, Yahya Zennayi
2020	J	`jnl`	Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture. J. Circuits Syst. Comput. Mohamed Najoui, Anas Hatim, Said Belkouch, Noureddine Chabini
2018	Misc	`conf`	Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection. ATSIP Lhoussein Mabrouk, Sylvain Huet, Dominique Houzet, Said Belkouch, Abdelkrim Hamzaoui, Yahya Zennayi
2018	—	`conf`	Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection. CIST Lhoussein Mabrouk, Dominique Houzet, Sylvain Huet, Said Belkouch, Abdelkrim Hamzaoui, Yahya Zennayi
2017	—	`conf`	Novel parallel Givens QR decomposition implementation on VLIW architecture with Efficient memory access for real time image processing applications. BDCA Mohamed Najoui, Anas Hatim, Said Belkouch
2017	J	`jnl`	VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing. J. Circuits Syst. Comput. Mohamed Najoui, Mounir Bahtat, Anas Hatim, Said Belkouch, Noureddine Chabini
2016	J	`jnl`	Efficient architecture for direct 8 × 8 2D DCT computations with earlier zigzag ordering. Multim. Tools Appl. Anas Hatim, Said Belkouch, Abderrahim Benslimane, Moha M'rabet Hassani, Tayeb Sadiki
2016	J	`jnl`	Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage. EURASIP J. Adv. Signal Process. Mounir Bahtat, Said Belkouch, Philippe Elleaume, Philippe Le Gall
2015	C	`conf`	Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders. AICCSA Noureddine Chabini, Said Belkouch
2015	C	`conf`	Real-time parallel implementation of road traffic radar video processing algorithms on a parallel architecture based on DSP and ARM processors. ISDA Abdessamad Klilou, François Bourzeix, Omar Bourja, Yahya Zennayi, Lhoussein Mabrouk, Said Belkouch
2014	—	`conf`	Fast enumeration-based modulo scheduling heuristic for VLIW architectures. ICM Mounir Bahtat, Said Belkouch, Philippe Elleaume, Phillipe Le Gall
2014	J	`jnl`	Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect. EURASIP J. Adv. Signal Process. Abdessamad Klilou, Said Belkouch, Philippe Elleaume, Philippe Le Gall, François Bourzeix, Moha M'rabet Hassani
2013	J	`jnl`	Design optimization of the quantization and a pipelined 2D-DCT for real-time applications. Multim. Tools Appl. Anas Hatim, Said Belkouch, Mohamed El Aakif, Moha M'rabet Hassani, Noureddine Chabini
2009	—	`conf`	FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding. SoCC Michael Guarisco, Hassan Rabah, Yves Berviller, Serge Weber, Said Belkouch
2007	—	`conf`	A CMOS High-Q LC Eight-Path Bandpass Filter for Wireless Broadband Applications. ICECS Ahmed El Oualkadi, Jean-Marie Paillot, Said Belkouch, Denis Flandre