Sai Rahul Chalamalasetti

39 papers A* 1A 4B 6Journal 10Unranked 18
YearRankTypeTitle / Venue / Authors
2024 — conf
Acceleration of Graph Neural Networks with Heterogenous Accelerators Architecture.
SC Workshops
Kaiwen Cao, Archit Gajjar, Liad Gerstman, Kun Wu, Sai Rahul Chalamalasetti, Aditya Dhakal, Giacomo Pedretti, Pavana Prakash, Wen-Mei Hwu, Deming Chen, Dejan S. Milojicic
2024 B conf
Opportunistic Energy-Aware Scheduling for Container Orchestration Platforms Using Graph Neural Networks.
CCGrid
Philipp Raith, Gourav Rattihalli, Aditya Dhakal, Sai Rahul Chalamalasetti, Dejan S. Milojicic, Eitan Frachtenberg, Stefan Nastic, Schahram Dustdar
2024 J jnl
Predicting Heterogeneity and Serverless Principles of Converged High-Performance Computing, Artificial Intelligence, and Workflows.
Computer
Pedro Bruel, Sai Rahul Chalamalasetti, Aditya Dhakal, Eitan Frachtenberg, Ninad Hogade, Rolando Pablo Hong Enriquez, Alok Mishra, Dejan S. Milojicic, Pavana Prakash, Gourav Rattihalli
2023 A conf
Kernel-as-a-Service: A Serverless Programming Model for Heterogeneous Hardware Accelerators.
Middleware
Tobias Pfandzelter, Aditya Dhakal, Eitan Frachtenberg, Sai Rahul Chalamalasetti, Darel Emmot, Ninad Hogade, Rolando Pablo Hong Enriquez, Gourav Rattihalli, David Bermbach, Dejan S. Milojicic
2021 — conf
A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems : (Invited Paper).
PEHC@SC
Sitao Huang, Kun Wu, Sai Rahul Chalamalasetti, Izzat El Hajj, Cong Xu, Paolo Faraboschi, Deming Chen
2021 — conf
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators.
ASP-DAC
Sitao Huang, Aayush Ankit, Plínio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong Eun Kim, Glaucimar Aguiar, Pedro Bruel, Sergey Serebryakov, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan, Deming Chen, Kaushik Roy, Wen-mei W. Hwu, Dejan S. Milojicic
2021 B conf
Resource Sharing and Security Implications on Machine Learning Inference Accelerators.
COMPSAC
Plínio Silveira, César Augusto Fonticielha De Rose, Avelino Francisco Zorzo, Miguel Gomes Xavier, Dejan S. Milojicic, Sai Rahul Chalamalasetti, Sergey Serebryakov
2020 J jnl
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM.
IEEE Trans. Computers
Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-Mei Hwu, Kaushik Roy
2019 B conf
Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures.
ICPE
Sitao Huang, Li-Wen Chang, Izzat El Hajj, Simon Garcia De Gonzalo, Juan Gómez-Luna, Sai Rahul Chalamalasetti, Mohamed El-Hadedy, Dejan S. Milojicic, Onur Mutlu, Deming Chen, Wen-mei W. Hwu
2019 — conf
FPGA Demonstrator of a Programmable Ultra-Efficient Memristor-Based Machine Learning Inference Accelerator.
ICRC
Martin Foltin, Glaucimar Aguiar, Rodrigo Antunes, Plínio Silveira, Gustavo Knuppe, Joao Ambrosi, Soumitra Chatterjee, Jitendra Onkar Kolhe, Sunil Lakshiminarashimha, Dejan S. Milojicic, John Paul Strachan, Craig Warner, Amit Sharma, Eddie Lee, Sai Rahul Chalamalasetti, Chris Brueggen, Charles Williams, Nathaniel Jansen, Felipe Saenz, Luis Federico Li
2019 J jnl
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM.
CoRR
Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-mei W. Hwu, Kaushik Roy
2019 A* conf
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference.
ASPLOS
Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-mei W. Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic
2019 J jnl
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference.
CoRR
Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-Mei Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic
2018 — conf
Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning.
ICRC
Joao Ambrosi, Aayush Ankit, Rodrigo Antunes, Sai Rahul Chalamalasetti, Soumitra Chatterjee, Izzat El Hajj, Guilherme Fachini, Paolo Faraboschi, Martin Foltin, Sitao Huang, Wen-Mei Hwu, Gustavo Knuppe, Sunil Vishwanathpur Lakshminarasimha, Dejan S. Milojicic, Mohan Parthasarathy, Filipe Ribeiro, Lucas Rosa, Kaushik Roy, Plínio Silveira, John Paul Strachan
2018 — conf
Regular Expression Matching with Memristor TCAMs for Network Security.
NANOARCH
Catherine E. Graves, Wen Ma, Xia Sheng, Brent Buchanan, Le Zheng, Sity Lam, Xuema Li, Sai Rahul Chalamalasetti, Lennie Kiyama, Martin Foltin, John Paul Strachan, Matthew P. Hardy
2018 — conf
Regular Expression Matching with Memristor TCAMs.
ICRC
Catherine E. Graves, Wen Ma, Xia Sheng, Brent Buchanan, Le Zheng, Sity Lam, Xuema Li, Sai Rahul Chalamalasetti, Lennie Kiyama, Martin Foltin, Matthew P. Hardy, John Paul Strachan
2017 — conf
Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp.
ReConFig
Pedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic
2017 — conf
Generalize or Die: Operating Systems Support for Memristor-Based Accelerators.
ICRC
Pedro Bruel, Sai Rahul Chalamalasetti, Chris I. Dalton, Izzat El Hajj, Alfredo Goldman, Catherine Graves, Wen-mei W. Hwu, Phil Laplante, Dejan S. Milojicic, Geoffrey Ndu, John Paul Strachan
2015 A conf
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only).
FPGA
Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti
2014 J jnl
High Level Programming for Heterogeneous Architectures.
CoRR
Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright
2014 B conf
High level programming framework for FPGAs in the data center.
FPL
Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright
2013 J jnl
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification.
SIGARCH Comput. Archit. News
Wim Vanderbauwhede, Anton Frolov, Sai Rahul Chalamalasetti, Martin Margala
2013 A conf
An FPGA memcached appliance.
FPGA
Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala
2013 J jnl
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
2013 A conf
High throughput filtering using FPGA-acceleration.
CIKM
Wim Vanderbauwhede, Anton Frolov, Leif Azzopardi, Sai Rahul Chalamalasetti, Martin Margala
2013 J jnl
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
2012 B conf
Evaluating FPGA-acceleration for real-time unstructured search.
ISPASS
Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, Mitch Wright, Parthasarathy Ranganathan
2012 J jnl
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application.
Int. J. Reconfigurable Comput.
Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala
2011 — conf
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks.
HPCS
Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala
2010 — conf
A C++-embedded Domain-Specific Language for programming the MORA soft processor array.
ASAP
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
2010 — conf
Design of self correcting radiation hardened digital circuits using decoupled ground bus.
ACM Great Lakes Symposium on VLSI
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2010 — conf
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths.
AHS
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2010 J jnl
Radiation-Hardened Reconfigurable Array With Instruction Roll-Back.
IEEE Embed. Syst. Lett.
Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
2009 — conf
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.
ACM Great Lakes Symposium on VLSI
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2009 B conf
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.
FPL
Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala
2009 — conf
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor.
AHS
Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
2009 — conf
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor.
ERSA
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
2008 — conf
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices.
ReConFig
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello
2008 — conf
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing.
SoCC
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello