Sai-Weng Sin - RankMe

145 papers C 15Journal 67Unranked 63

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	26.5 An Inductor-at-Middle Hybrid Buck Converter with Shared Power-Signal Path for Distributed Vertical Power Delivery. ISSCC Zhongyao Zhu, Junwei Huang, Zhibang Song, Zhewen Yu, Shousheng Han, Sai-Weng Sin, Yan Lu
2026	—	`conf`	A 103.9dB-SFDR 83.8dB-SNDR 3MHz-BW Multi-Bit Quadratic-Exponential Noise-Coupled IDSM with High Tolerance to DAC Non-Linearity. ISSCC Zhensheng Li, Biao Wang, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin
2026	J	`jnl`	A 6.4-GS/s, 200-MHz BW 77.3-dB DR 71.5-dB SNDR 2× TI Extrapolated CT DSM Employing Broadband Hybrid-Inputs Adder and Nonlinearity-Suppression DAC Encoder. IEEE J. Solid State Circuits Yuekai Liu, Yichen Jin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Zhichao Tan, Guoxing Wang, Liang Qi
2026	J	`jnl`	Analysis and Design of a Pipelined MASH Continuous-Time Delta-Sigma Modulator With 15.4 MHz-BW and 82.6 dB-SNDR. IEEE Trans. Circuits Syst. I Regul. Pap. Xinyu Qin, Yichen Jin, Mingqiang Guo, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi
2025	—	`conf`	A 0.0022 mm CICC Tao Lu, Zixiang Liu, Hao Yang, Sai-Weng Sin, Robert Bogdan Staszewski, Fujiang Lin, Liheng Lou, Yizhe Hu
2025	—	`conf`	A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification. CICC Haoyu Li, Boyang Wang, Hongjiang Chen, Sai-Weng Sin, Yutao Peng, Xizhu Peng, He Tang, Chao Fan, Liang Qi, Rui Paulo Martins, Mingqiang Guo
2025	J	`jnl`	A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering. IEEE J. Solid State Circuits Ke Li, Haoyu Gong, Xianyu Congzhou, Zhensheng Li, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin
2025	J	`jnl`	A 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by a DC-DC Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Haoyu Gong, Ke Li, Wen-Liang Zeng, Mingqiang Guo, Chi-Seng Lam, Shulin Zhao, Rui Paulo Martins, Sai-Weng Sin
2025	J	`jnl`	A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation. IEEE Trans. Circuits Syst. I Regul. Pap. Ran Zhang, Xueru Cen, Ka-Fai Un, Mingqiang Guo, Liang Qi, Rui Paulo Martins, Sai-Weng Sin
2025	C	`conf`	A 4-Phase Adaptive On-Time Controlled Buck Converter With Auto-Synchronized Dynamic Frequency and Transient-Enhancement Techniques. ISCAS Zhiming He, Sai-Weng Sin, Rui Paulo Martins, Yan Lu
2025	J	`jnl`	A 7-Bit 1.41-GS/s 2-Bit/Cycle Precharge-Advancing SAR ADC With Fast Discharge Comparator. IEEE Trans. Circuits Syst. II Express Briefs Zixiang Liu, Tao Lu, Sai-Weng Sin, Robert Bogdan Staszewski, Liheng Lou, Yizhe Hu
2025	J	`jnl`	A Dual-Inductor Quad-Path Hybrid Buck (2L4PHB) Converter With Reduced Inductor Current. IEEE J. Solid State Circuits Wen-Liang Zeng, Guigang Cai, Yan Lu, Sai-Weng Sin, Rui Paulo Martins, Chi-Seng Lam
2025	J	`jnl`	A GaN Driver IC With Asymmetrical dV/dt Current Clamping Level Shifter and Logic-Based Adaptive Deadtime Control. IEEE Trans. Circuits Syst. I Regul. Pap. Dajun Zhou, Tianqi Liu, Zhongyao Zhu, Sai-Weng Sin, Rui Paulo Martins, Yan Lu
2024	—	`conf`	A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS. CICC Xinyu Qin, Yichen Jin, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi
2024	—	`conf`	A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering. CICC Ke Li, Xianyu Congzhou, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin
2024	—	`conf`	A 5.76GS/s 180MHz-BW 74.1dB-DR 2x TI Extrapolated CT DSM with Broadband Hybrid-Inputs Current-Mode Adder in 28nm CMOS. A-SSCC Yuekai Liu, Meng Guo, Yichen Jin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Zhichao Tan, Liang Qi
2024	—	`conf`	A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter. CICC Haoyu Gong, Wen-Liang Zeng, Mingqiang Guo, Chi-Seng Lam, Shulin Zhao, Rui Paulo Martins, Sai-Weng Sin
2024	C	`conf`	A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. ISCAS Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, Rui Paulo Martins, Franco Maloberti, Sai-Weng Sin
2024	—	`conf`	Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing. ICTA Ran Zhang, Ka-Fai Un, Zhensheng Li, Mingqiang Guo, Liang Qi, Rui Paulo Martins, Sai-Weng Sin
2023	J	`jnl`	A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA. IEEE Trans. Circuits Syst. I Regul. Pap. Gaofeng Tan, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi
2023	J	`jnl`	A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing. IEEE Trans. Circuits Syst. I Regul. Pap. Mingqiang Guo, Liang Qi, Weibing Zhao, Gang Xiao, Rui Paulo Martins, Sai-Weng Sin
2023	—	`conf`	A 12V-lnput 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter. ISSCC Wen-Liang Zeng, Guigang Cai, Chon-Fai Lee, Chi-Seng Lam, Yan Lu, Sai-Weng Sin, Rui Paulo Martins
2023	J	`jnl`	A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward. IEEE J. Solid State Circuits Shulin Zhao, Mingqiang Guo, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins, Sai-Weng Sin
2023	J	`jnl`	A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications. IEEE J. Solid State Circuits Caolei Pan, Wen-Liang Zeng, Chi-Seng Lam, Sai-Weng Sin, Chenchang Zhan, Rui Paulo Martins
2023	J	`jnl`	A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. Yue Hu, Yuekai Liu, Xinyu Qin, Yan Liu, Mingqiang Guo, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi
2023	J	`jnl`	A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. IEEE Trans. Circuits Syst. II Express Briefs Kaiquan Chen, Biao Wang, Yan Liu, Fan Ye, Sai-Weng Sin, Guoxing Wang, Yong Lian, Liang Qi
2023	J	`jnl`	IoT Cloud-Edge Reconfigurable Mixed-Signal Smart Meter Platform for Arc Fault Detection. IEEE Internet Things J. Ya-Jie Wu, Ricardo Brito, Wai-Hei Choi, Chi-Seng Lam, Man-Chung Wong, Sai-Weng Sin, Rui Paulo Martins
2023	J	`jnl`	On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs Jingying Zhang, Sai-Weng Sin, Yan Liu, Fan Ye, Guoxing Wang, Maurits Ortmanns, Liang Qi
2023	—	`conf`	Weightings in Incremental ADCs: A Tutorial Review. CICC Ruiqi Gao, Mingqiang Guo, Sai-Weng Sin, Liang Qi, Biao Wang, Guoxing Wang, Rui Paulo Martins
2022	—	`conf`	A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. CICC Mingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao, Rui Paulo Martins
2022	C	`conf`	A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. ISCAS Ke Li, Sai-Weng Sin, Liang Qi, Weibing Zhao, Guoxing Wang, Rui Paulo Martins
2022	J	`jnl`	An FPGA-Based Self-Reconfigurable Arc Fault Detection System for Smart Meters. IEEE Trans. Circuits Syst. II Express Briefs Ya-Jie Wu, Wai-Hei Choi, Chi-Seng Lam, Man-Chung Wong, Sai-Weng Sin, Rui Paulo Martins
2022	J	`jnl`	Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs Mingqiang Guo, Sai-Weng Sin, Liang Qi, Dengke Xu, Guoxing Wang, Rui Paulo Martins
2022	J	`jnl`	High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. Danfeng Zhai, Wenning Jiang, Xinru Jia, Jingchao Lan, Mingqiang Guo, Sai-Weng Sin, Fan Ye, Qi Liu, Junyan Ren, Chixiao Chen
2022	J	`jnl`	Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs Liang Qi, Yuekai Liu, Sai-Weng Sin, Xinpeng Xing, Guoxing Wang, Maurits Ortmanns, Rui Paulo Martins
2021	—	`conf`	A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCM. A-SSCC Wen-Liang Zeng, Caolei Pan, Chi-Seng Lam, Sai-Weng Sin, Chenchang Zhan, Rui Paulo Martins
2021	J	`jnl`	A Time-Interleaved 2 IEEE J. Solid State Circuits Dongyang Jiang, Liang Qi, Sai-Weng Sin, Franco Maloberti, Rui Paulo Martins
2021	—	`conf`	Advances in Continuous-time MASH ΔΣ Modulators. ASICON Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang
2021	—	`conf`	Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs. ISOCC Mingqiang Guo, Sai-Weng Sin, Rui Paulo Martins
2021	J	`jnl`	Bird's-eye view of analog and mixed-signal chips for the 21st century. Int. J. Circuit Theory Appl. Rui Paulo Martins, Pui-In Mak, Chi-Hang Chan, Jun Yin, Yan Zhu, Yong Chen, Yan Lu, Man-Kay Law, Sai-Weng Sin
2021	C	`conf`	Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. ISCAS Xinyu Qin, Jingying Zhang, Liang Qi, Sai-Weng Sin, Rui Paulo Martins, Guoxing Wang
2020	J	`jnl`	A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration. IEEE J. Solid State Circuits Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
2020	J	`jnl`	A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application. IEEE Trans. Circuits Syst. Wen-Liang Zeng, Yuan Ren, Chi-Seng Lam, Sai-Weng Sin, Weng-Keong Che, Ran Ding, Rui Paulo Martins
2020	J	`jnl`	A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications. IEEE Access Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
2020	—	`conf`	A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2 VLSI Circuits Dongyang Jiang, Liang Qi, Sai-Weng Sin, Franco Maloberti, Rui Paulo Martins
2020	J	`jnl`	A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. IEEE J. Solid State Circuits Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns
2020	J	`jnl`	A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery. IEEE Trans. Circuits Syst. II Express Briefs Wen-Liang Zeng, Edoardo Bonizzoni, Chi-Wa U, Chi-Seng Lam, Sai-Weng Sin, U. Fat Chio, Franco Maloberti, Rui Paulo Martins
2020	J	`jnl`	Analysis, Design and Control of an Integrated Three-Level Buck Converter under DCM Operation. J. Circuits Syst. Comput. Wen-Ming Zheng, Wen-Liang Zeng, Chi-Wa U, Chi-Seng Lam, Yan Lu, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins
2020	J	`jnl`	Digital Battery Management Unit With Built-In Resistance Compensation, Modulated Frequency Detection and Multi-Mode Protection for Fast, Efficient and Safe Charging. IEEE Trans. Circuits Syst. Ji-Xuan Li, Sai-Weng Sin, U. Fat Chio, Ya-Jie Wu, Chi-Seng Lam, Rui Paulo Martins
2020	J	`jnl`	LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration. IEEE Trans. Circuits Syst. Hanyu Wang, Sai-Weng Sin, Chi-Seng Lam, Franco Maloberti, Rui Paulo Martins
2019	—	`conf`	A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. A-SSCC Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2019	—	`conf`	A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration. CICC Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
2019	—	`conf`	A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing. VLSI Circuits Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
2019	J	`jnl`	A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. IEEE J. Solid State Circuits Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2019	—	`conf`	A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. ISSCC Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns
2019	—	`conf`	A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. A-SSCC Junhao Liang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, Hanjun Jiang
2019	J	`jnl`	Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. IEEE Trans. Very Large Scale Integr. Syst. Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2019	J	`jnl`	An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. IEEE J. Solid State Circuits U-Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, Rui Paulo Martins
2019	J	`jnl`	Design of KY Converter With Constant On-Time Control Under DCM Operation. IEEE Trans. Circuits Syst. II Express Briefs Wen-Liang Zeng, Zi-Yang Lin, Chi-Seng Lam, Man-Kay Law, Sai-Weng Sin, Franco Maloberti, Man-Chung Wong, Rui Paulo Martins
2019	—	`conf`	Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. ASICON Liang Qi, Sai-Weng Sin, Rui Paulo Martins
2018	J	`jnl`	A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches. IEEE Trans. Circuits Syst. II Express Briefs Da Feng, Edoardo Bonizzoni, Franco Maloberti, Sai-Weng Sin, Rui Paulo Martins
2018	J	`jnl`	A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current. IEEE Trans. Circuits Syst. II Express Briefs Jiaji Mao, Mingqiang Guo, Sai-Weng Sin, Rui Paulo Martins
2018	J	`jnl`	A 220-MHz Bondwire-Based Fully-Integrated KY Converter With Fast Transient Response Under DCM Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Wen-Liang Zeng, Chi-Seng Lam, Sai-Weng Sin, Franco Maloberti, Man-Chung Wong, Rui Paulo Martins
2018	—	`conf`	A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. VLSI Circuits Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2018	C	`conf`	A Power Quality Indexes Measurement System Platform with Remote Alarm Notification. IECON Jianyang Deng, Chi-Seng Lam, Man-Chung Wong, Lei Wang, Sai-Weng Sin, Rui Paulo Martins
2018	J	`jnl`	A Reconfigurable and Extendable Digital Architecture for Mixed Signal Power Electronics Controller. IEEE Trans. Circuits Syst. II Express Briefs Ya-Jie Wu, Chi-Seng Lam, Man-Chung Wong, Sai-Weng Sin, Rui Paulo Martins
2018	—	`conf`	An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. A-SSCC U. Fat Chio, Kuo-Chih Wen, Sai-Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, Rui Paulo Martins
2018	C	`conf`	Design and Control of An Integrated 3-Level Boost Converter under DCM Operation. ISCAS Yiwei Tan, Chi-Seng Lam, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins
2018	J	`jnl`	Quick and cost-efficient A/D converter static characterization using low-precision testing signal. Microelectron. J. Wei Wei Qin, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2018	J	`jnl`	Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM. J. Electr. Comput. Eng. Yu-Jun Mao, Chi-Seng Lam, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins
2017	J	`jnl`	A 12b 180MS/s 0.068mm IEEE Trans. Circuits Syst. I Regul. Pap. Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2017	—	`conf`	A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. A-SSCC U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2017	J	`jnl`	A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2017	J	`jnl`	A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2017	—	`conf`	A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC. ISIE Xia Du, Chi-Seng Lam, Sai-Weng Sin, Man-Kay Law, Franco Maloberti, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	A sub-1V 78-nA bandgap reference with curvature compensation. Microelectron. J. Ziyang Luo, Yan Lu, Mo Huang, Junmin Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. Arshad Hussain, Sai-Weng Sin, Chi-Hang Chan, Ben Seng-Pan U, Franco Maloberti, Rui Paulo Martins
2017	C	`conf`	CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. IECON Chi-Wa U, Chi-Seng Lam, Man-Kay Law, Sai-Weng Sin, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	Metastablility in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Boris Murmann, Seng-Pan U, Rui Paulo Martins
2017	J	`jnl`	Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A 12b 180MS/s 0.068mm ESSCIRC Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2016	J	`jnl`	A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. IEEE J. Solid State Circuits Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications. ISIC Wei Li, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2016	J	`jnl`	A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. IEEE Trans. Circuits Syst. II Express Briefs Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller. A-SSCC Yuan Ren, Sai-Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. ESSCIRC Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U. Fat Chio, Sai-Weng Sin, Rui Paulo Martins
2016	J	`jnl`	Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Wing-Hung Ki
2016	J	`jnl`	Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2015	—	`conf`	20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. ISSCC Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2015	—	`conf`	26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. ISSCC Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2015	—	`conf`	A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. A-SSCC Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2015	J	`jnl`	Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters. IEEE J. Emerg. Sel. Topics Circuits Syst. Da Feng, Franco Maloberti, Sai-Weng Sin, Rui Paulo Martins
2015	J	`jnl`	Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2014	C	`conf`	Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. ISCAS Da Feng, Franco Maloberti, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2014	J	`jnl`	Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2013	C	`conf`	A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2013	J	`jnl`	A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. IEEE J. Solid State Circuits Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2013	J	`jnl`	A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. IEEE J. Solid State Circuits Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2013	—	`conf`	A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation. MWSCAS Li Ding, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2013	C	`conf`	A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. ISCAS Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2012	—	`conf`	A 0.024 mm ESSCIRC Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins
2012	—	`conf`	A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. APCCAS Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	C	`conf`	A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. ISCAS Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2012	—	`conf`	A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. ESSCIRC Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins
2012	—	`conf`	A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. CICC Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2012	—	`conf`	A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	—	`conf`	A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	J	`jnl`	A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. IEEE J. Solid State Circuits Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2012	—	`conf`	A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. APCCAS Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	—	`conf`	A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. APCCAS Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2012	J	`jnl`	An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2012	—	`conf`	An ELD tracking compensation technique for active-RC CT ΣΔ modulators. MWSCAS Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2011	—	`conf`	A 0.024mm ISSCC He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2011	—	`conf`	A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. A-SSCC Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2011	—	`conf`	A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2011	—	`conf`	A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2011	—	`conf`	A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2011	—	`conf`	Hybrid loopfilter sigma-delta modulator with NTF zero compensation. ISOCC Arshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2010	J	`jnl`	1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. IET Circuits Devices Syst. Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2010	J	`jnl`	A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2010	—	`conf`	A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. ICECS Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	J	`jnl`	A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	—	`conf`	A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. APCCAS Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2010	C	`conf`	A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	—	`conf`	An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
2010	—	`conf`	An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. APCCAS Li Ding, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2010	—	`conf`	An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang
2010	J	`jnl`	Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. IEEE Trans. Circuits Syst. II Express Briefs U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
2010	J	`jnl`	Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	C	`conf`	A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	—	`conf`	A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. ICECS Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	—	`conf`	A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. APCCAS He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2008	—	`conf`	A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique. APCCAS Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2008	—	`conf`	A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. APCCAS U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
2008	J	`jnl`	Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. IEEE Trans. Circuits Syst. I Regul. Pap. Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2008	J	`jnl`	Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. IEEE Trans. Circuits Syst. II Express Briefs Sai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins
2006	C	`conf`	A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. ISCAS Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2006	C	`conf`	A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. ISCAS Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2005	—	`conf`	A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. ISCAS (2) Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2005	—	`conf`	A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. ISCAS (2) Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2004	—	`conf`	A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. ISCAS (1) Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
2004	J	`jnl`	Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects. IEEE Trans. Instrum. Meas. Seng-Pan U., Sai-Weng Sin, Rui Paulo Martins
2003	—	`conf`	Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals. ICASSP (6) Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
2003	—	`conf`	Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. ISCAS (1) Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca