Safeen Huda - RankMe

21 papers A* 3A 3B 2Misc 2Journal 9Unranked 2

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	HALO: Hardware-Aware Quantization with Low Critical-Path-Delay Weights for LLM Acceleration. AAAI Rohan Juneja, Shivam Aggarwal, Safeen Huda, Tulika Mitra, Li-Shiuan Peh
2025	J	`jnl`	HALO: Hardware-aware quantization with low critical-path-delay weights for LLM acceleration. CoRR Rohan Juneja, Shivam Aggarwal, Safeen Huda, Tulika Mitra, Li-Shiuan Peh
2024	J	`jnl`	Attamba: Attending To Multi-Token States. CoRR Yash Akhauri, Safeen Huda, Mohamed S. Abdelfattah
2024	Misc	`conf`	Resiliency at Scale: Managing Google's TPUv4 Machine Learning Supercomputer. NSDI Yazhou Zu, Alireza Ghaffarkhah, Hoang-Vu Dang, Brian Towles, Steven Hand, Safeen Huda, Adekunle Bello, Alexander Kolbasov, Arash Rezaei, Dayou Du, Steve Lacy, Hang Wang, Aaron Wisner, Chris Lewis, Henri Bahini
2024	A*	`conf`	ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. EMNLP Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah
2024	J	`jnl`	ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. CoRR Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah
2022	A*	`conf`	A full-stack search technique for domain optimized deep learning accelerators. ASPLOS Dan Zhang, Safeen Huda, Ebrahim M. Songhori, Kartik Prabhu, Quoc V. Le, Anna Goldie, Azalia Mirhoseini
2022	A	`conf`	Learning to Design Accurate Deep Learning Accelerators with Inaccurate Multipliers. DATE Paras Jain, Safeen Huda, Martin Maas, Joseph E. Gonzalez, Ion Stoica, Azalia Mirhoseini
2021	J	`jnl`	A Full-stack Accelerator Search Technique for Vision Applications. CoRR Dan Zhang, Safeen Huda, Ebrahim M. Songhori, Quoc V. Le, Anna Goldie, Azalia Mirhoseini
2020	J	`jnl`	Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2017	J	`jnl`	Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Safeen Huda, Jason Helge Anderson
2016	J	`jnl`	Hybrid LUT/Multiplexer FPGA Logic Architectures. IEEE Trans. Very Large Scale Integr. Syst. S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson
2016	—	`conf`	Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques. ISPD Safeen Huda, Jason Helge Anderson
2016	A	`conf`	Towards PVT-Tolerant Glitch-Free Operation in FPGAs. FPGA Safeen Huda, Jason Helge Anderson
2014	J	`jnl`	A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions. IEEE Trans. Circuits Syst. I Regul. Pap. Aynaz Vatankhahghadim, Safeen Huda, Ali Sheikholeslami
2014	Misc	`conf`	On Hard Adders and Carry Chains in FPGAs. FCCM Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
2014	A	`conf`	Optimizing effective interconnect capacitance for FPGA power reduction. FPGA Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
2013	J	`jnl`	A Novel STT-MRAM Cell With Disturbance-Free Read Operation. IEEE Trans. Circuits Syst. I Regul. Pap. Safeen Huda, Ali Sheikholeslami
2013	B	`conf`	Charge recycling for power reduction in FPGA interconnect. FPL Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
2010	—	`conf`	Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. ISSCC David Halupka, Safeen Huda, William Song, Ali Sheikholeslami, Koji Tsunoda, Chikako Yoshida, Masaki Aoki
2009	B	`conf`	Clock gating architectures for FPGA power reduction. FPL Safeen Huda, Muntasir Mallick, Jason Helge Anderson