Saeideh Shirinzadeh

27 papers A* 1A 4C 5Misc 1Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2025 C conf
A Comprehensive Synthesis and Verification Approach for RRAM-Based Neuromorphic Computing.
DSD
Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler
2025 — conf
Fast and Scalable MAGIC-Based Wallace Tree Multiplier for In-Memory Computing.
CCMCC
Saeideh Nabipour, Kamalika Datta, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
2024 Misc conf
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures.
VLSID
Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler
2024 J jnl
ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars.
ACM Trans. Embed. Comput. Syst.
Kousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
2024 — conf
Towards Formal Verification for MAC-based In-Memory Computing.
ATS
Fatemeh Shirinzadeh, Kamalika Datta, Saeideh Shirinzadeh, Abhoy Kole, Rolf Drechsler
2023 — conf
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars.
ASP-DAC
Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
2023 — conf
Verification of In-Memory Logic Design using ReRAM Crossbars.
NEWCAS
Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
2022 J jnl
Parallel Computing of Graph-based Functions in ReRAM.
ACM J. Emerg. Technol. Comput. Syst.
Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
2022 C conf
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications.
VLSI-SoC
Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta, Rolf Drechsler
2022 C conf
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles.
DSD
Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler
2020 C conf
Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars.
ISCAS
Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
2019 — conf
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing.
NANOARCH
Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler
2019 — conf
Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits.
ISVLSI
Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
2018 — conf
Logic Design Using Memristors: An Emerging Technology.
ISMVL
Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler
2018 — conf
Logic Synthesis for In-memory Computing Using Resistive Memories.
ISVLSI
Saeideh Shirinzadeh, Rolf Drechsler
2018 J jnl
Logic Synthesis for RRAM-Based In-Memory Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
2018 — —
Synthesis and optimization for logic-in-memory computing using memristive devices.
Saeideh Shirinzadeh
2017 J jnl
A PLiM Computer for the Internet of Things.
Computer
Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli
2017 A conf
An adaptive prioritized
GECCO
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
2017 A conf
Endurance management for resistive Logic-In-Memory computing architectures.
DATE
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
2017 J jnl
Synthesis of optical circuits using binary decision diagrams.
Integr.
Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
2016 A* conf
An MIG-based compiler for programmable logic-in-memory architectures.
DAC
Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
2016 — conf
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm.
GECCO (Companion)
Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
2016 A conf
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs.
DATE
Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
2016 C conf
Multi-objective BDD optimization for RRAM based circuit design.
DDECS
Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
2015 A conf
Multi-Objective BDD Optimization with Evolutionary Algorithms.
GECCO
Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
2013 J jnl
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design.
J. Electron. Test.
Rahebeh Niaraki Asli, Saeideh Shirinzadeh