Saeid Daneshgar

15 papers C 2Journal 8Unranked 5
YearRankTypeTitle / Venue / Authors
2022 J jnl
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μA
IEEE J. Solid State Circuits
Saeid Daneshgar, Hao Li, Taehwan Kim, Ganesh Balamurugan
2018 — conf
A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO.
ISSCC
Saeid Daneshgar, Kaushik Dasgupta, Chintan Thakkar, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper
2018 — conf
A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO.
ISSCC
Shinwon Kang, Chintan Thakkar, Nathan Narevsky, Kaushik Dasgupta, Saeid Daneshgar, James E. Jaussi, Bryan Casper
2018 J jnl
A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS.
IEEE J. Solid State Circuits
Kaushik Dasgupta, Saeid Daneshgar, Chintan Thakkar, Shinwon Kang, Anandaroop Chakrabarti, Shuhei Yamada, Nathan Narevsky, Debabani Choudhury, James E. Jaussi, Bryan Casper
2017 — conf
A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS.
ESSCIRC
Kaushik Dasgupta, Saeid Daneshgar, Chintan Thakkar, Kunal Datta, James E. Jaussi, Bryan Casper
2015 J jnl
A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process.
IEEE J. Solid State Circuits
Kristian N. Madsen, Timothy D. Gathman, Saeid Daneshgar, Thomas C. Oh, James Chingwei Li, James F. Buckwalter
2014 J jnl
Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers.
IEEE J. Solid State Circuits
Saeid Daneshgar, Zach Griffith, Munkyo Seo, Mark J. W. Rodwell
2014 J jnl
Millimeter-Wave Series Power Combining Using Sub-Quarter-Wavelength Baluns.
IEEE J. Solid State Circuits
Hyun-Chul Park, Saeid Daneshgar, Zach Griffith, Miguel Urteaga, Byung-Sung Kim, Mark J. W. Rodwell
2011 J jnl
Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part II: Design Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Saeid Daneshgar, Oscar De Feo, Michael Peter Kennedy
2010 C conf
A qualitative analysis of a complementary differential LC injection-locked frequency divider based on direct injection.
ISCAS
Saeid Daneshgar, Michael Peter Kennedy
2010 J jnl
Analysis and Design of Injection-Locked Frequency Dividers by Means of a Phase-Domain Macromodel.
IEEE Trans. Circuits Syst. I Regul. Pap.
Paolo Maffezzoni, Dario D'Amore, Saeid Daneshgar, Michael Peter Kennedy
2010 C conf
Estimating the locking range of analog dividers through a phase-domain macromodel.
ISCAS
Paolo Maffezzoni, Dario D'Amore, Saeid Daneshgar, Michael Peter Kennedy
2010 J jnl
Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part I: Qualitative Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Saeid Daneshgar, Oscar De Feo, Michael Peter Kennedy
2008 — conf
Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis.
ICECS
Saeid Daneshgar, Michael Peter Kennedy
2007 — conf
Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis.
ECCTD
Mohammad M. Ghahramani, Saeid Daneshgar, Michael Peter Kennedy, Oscar De Feo