Sadegh Yazdanshenas

18 papers A 2B 3Journal 10Unranked 3
YearRankTypeTitle / Venue / Authors
2025 B conf
Routing Struggle: A Metric to Quantify Routability.
FPL
Sadegh Yazdanshenas, Jeffrey Chromczak
2020 J jnl
FPGA Logic Block Architectures for Efficient Deep Learning Inference.
ACM Trans. Reconfigurable Technol. Syst.
Mohamed Eldafrawy, Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
2019 J jnl
COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures.
ACM Trans. Reconfigurable Technol. Syst.
Sadegh Yazdanshenas, Vaughn Betz
2019 A conf
Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs.
FPGA
Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz
2019 J jnl
The Costs of Confidentiality in Virtualized FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Sadegh Yazdanshenas, Vaughn Betz
2018 B conf
Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs.
FPL
Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
2018 J jnl
Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs.
ACM Trans. Reconfigurable Technol. Syst.
Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz
2018 — conf
Improving Confidentiality in Virtualized FPGAs.
FPT
Sadegh Yazdanshenas, Vaughn Betz
2018 J jnl
Interconnect Solutions for Virtualized Field-Programmable Gate Arrays.
IEEE Access
Sadegh Yazdanshenas, Vaughn Betz
2018 J jnl
You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference.
ACM Trans. Reconfigurable Technol. Syst.
Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz
2017 — conf
Automatic circuit design and modelling for heterogeneous FPGAs.
FPT
Sadegh Yazdanshenas, Vaughn Betz
2017 A conf
Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration.
FPGA
Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz
2017 B conf
Quantifying and mitigating the costs of FPGA virtualization.
FPL
Sadegh Yazdanshenas, Vaughn Betz
2016 J jnl
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays.
IEEE Trans. Very Large Scale Integr. Syst.
Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi
2016 — conf
High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs.
FPT
Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz
2015 J jnl
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices.
IEEE Trans. Very Large Scale Integr. Syst.
Sadegh Yazdanshenas, Hossein Asadi, Behnam Khaleghi
2014 J jnl
Coding Last Level STT-RAM Cache for High Endurance and Low Power.
IEEE Comput. Archit. Lett.
Sadegh Yazdanshenas, Marzieh Ranjbar Pirbasti, Mahdi Fazeli, Ahmad Patooghy
2014 J jnl
Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices.
IEEE Trans. Circuits Syst. II Express Briefs
Sadegh Yazdanshenas, Hossein Asadi